As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses tophysical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute astream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRUreplacement. If pages must be brought in from disk, increment the next largest page number.TLBPage TableDecimal 4669 2227 13916 34587 48870 12608 49225hex 0x123d 0x08b3 0x365c 0x871b 0xbee6 0x3140 0xc049Valid1110Index0123(a) For each access shown above, list456789abTagOxb0x70x30x4Valid100111010011▪ whether the access is a hit or miss in the TLB,▪ whether the access is a hit or miss in the page table,whether the access is a page fault,the updated state of the TLB.Physical PageNumber12469Time Since LastAccess4137Physical Page or in Disk5DiskDisk6911Disk4DiskDisk312(b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a largerpage size? What are some of the disadvantages?

Name: As described in COD Section 5.7 (Virtual memory), virtual memory uses
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Description: As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses tophysical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data const

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As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. Decimal 4669 hex TLB Page Table 2227 13916 34587 48870 12608 49225 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 (a) For each access shown above, list 123 4 5 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, ▪ the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4 1 3 7 Physical Page or in Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3 12 (b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages?

As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. Decimal 4669 hex TLB Page Table 2227 13916 34587 48870 12608 49225 0x123d 0x08b3 0x365c 0x871b Oxbee6 0x3140 0xc049 Valid 1 1 1 0 Index 0 (a) For each access shown above, list 123 4 5 6 7 8 9 a b Tag Oxb Ox7 0x3 0x4 Valid 1 0 0 1 1 1 0 1 0 0 1 1 ▪ whether the access is a hit or miss in the TLB, ▪ whether the access is a hit or miss in the page table, ▪ whether the access is a page fault, ▪ the updated state of the TLB. Physical Page Number 12 4 6 9 Time Since Last Access 4 1 3 7 Physical Page or in Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3 12 (b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 13 bits wide.The cache is 4-way set associative (E = 4), with a 4-byte block size(B = 4) and eight sets (S = 8).Consider the following cache state. All addresses, tags, and valuesare given in hexadecimal format. The Index column contains the set index for each set of four lines. The Tag columns contain the tag value for each line. The V columns contain the valid bit for each line. The Bytes 0−3 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size (C) of this cache in bytes?B. The box that follows shows the format of an address (1 bit perbox). Indicate (by labeling the diagram) the fields that would beused to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tag
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system. Virtual Address (bits) Physical DRAMInstalled Page Size PTE Size (byte) 43 16 GiB 4 KiB 4 For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table? Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB? An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss?
A computer uses virtual memory, and a new solid-state drive (SSD) as space for paging. Refer to the last ppt file. In the case presented there, the hard disk drive (HDD) required 25 ms to read in a page, and a rate of 1 page fault per 1000 references introduced a 250 slowdown. If the SSD offers a time of only 80 µs, what is the slowdown in performance caused by 1 pf per 1000 references (you are not concerned with dirty vs. clean pages). What is the maximum rate of page faults you can accept if you want no more than a 5% slowdown in execution using virtual memory? Know your metric prefixes and symbols for time: s for seconds, ms for milliseconds, µs for microseconds, ns for nanoseconds.
Suppose that immediately following the two read operations of question 1,the program does read operations on the following memory addresses (e.g., with “lb”or “lw” instructions): 148, 224, 556, 248 (again), 6728, 1312 (again), and 128.Assuming the cache was empty prior to the read operations of question 1, state whichof these read operations will result in cache hits, assuming a 2-way set-associativecache with a total capacity of 4 eight-word blocks and LRU replacement in each set. Suppose that a program does read operations on the following memory addresses (e.g., with “lb” or “lw” instructions): 248, 1312. Give the number of the memory block that each of these addresses belongs to, for each of the following memory block sizes. A. block size of one word (4 bytes) B. block size of eight words (32 bytes) just do the first part
Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size:a) Determine how many bytes the offset field is.Measure the tag field's width and height in pixels (b).
Consider a virtual memory system that can address a total of 32 bytes. You have unlimited hard disk space, but are limited to only 16MB of semiconductor (physical) memory. Assume that virtual and physical pages are each 4 KB in size. What is the total size of the page table in bytes? (Assume that, in addition to the physical page number, each page table entry also contains some status information in the form of a valid bit (V) and a dirty bit (D)).
Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 1. Buff ers are employed between diff erent levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buff ers needed between L1 and L2 caches, as well as L2 cache and memory.2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), confi guration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.Consider the following program and cache behaviors. Data Reads per1000 Instructions Data Writes per1000 Instructions Instruction…
Assume there are three small caches, each consisting of four one word blocks. One cache isfully associative, a second is two way set associative, and the third is direct mapped. Find thenumber of misses for each cache organization given the following sequence of block addresses:1,7, 6, 5, 1, and 7.
I ONLY NEED 3 AND 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: Prog1 request 80KB, prog2 request 16KB, Prog3 request 140KB Prog1 finish, Prog3 finish; Prog4 request 80KB, Prog5 request 120kb Use first match and best match to deal with this sequence (from high address when allocated) (1)Draw allocation state when prog1,2,3 are loaded into memory? (2)Draw allocation state when prog1, 3 finish? (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish (4) Which algorithm is suitable for this sequence ? Describe the allocation process?
CA_10 Let the virtual address be V bits and the virtual addtess space be byte-addressable, the page size be P KB (and P is a power of 2), and the the main memory size be MM MB(where [MM MB]) is divide into [P KB]). (d)How many of the virtual memory bits need to be translated? (e) How many bits will be produced if the virtual-to-pyysical address translation is "successful" (f) How many bits does a physical address have, and how are each of these bits obtained?
Consider the dynamic memory layout shown below (the shaded blocks are already allocated). Draw to what the free memory layouts would be after satisfying requests for (in order) memory blocks of size 195K, 410K, 262K, and 385K. 500 KB 600 KB 590 KB 700 KB 480 KB Draw one memory layout for the worst-fit, best-fit algorithm, and one for first-fit. [02 Marks] Which algorithm makes the efficient use of the memory? Why? [01 Marks] Also indicate which type of fragmentation will occur and why? [01 Marks]