6.12 Write a behavioral-style Verilog module Vr2to4decp_b for the 2- to-4 binary decoder with polarity control shown in Figure 6-3. Use a vector I[1:0] for the select inputs, and a vector Y[0:3] for the outputs. Be sure that your code does not create an “inferred latch."

What are the shortcomings of one dimensional parity error detection scheme? And discuss the advantages of Two-dimensional parity over single parity scheme?

Let A = ajao and B = b¡bo be two-bit binary numbers. A and B can take on values from 0 to 3 (for example, A = 2 when a1ao = 10. Let C be a two bit binary number whose value equals the magnitude of the difference A – B. We have C = c1c0 = |A – B|. (This means that if B is larger than A then you consider B-A.) You are to design a circuit which accepts A and B (i.e., a¡ aob¡bo) as inputs and outputs the result C = c¡c0. The circuit thus has four inputs and two outputs. For example, the circuit should output c1co = 10 when ajao = 01 and bibo = 11 (C = 2 when A = 1 and B = 3). - Your pre-lab needs to include all items requested in the following steps (plus those requested in the pre-lab handout): 1. After reading through the complete lab, write a description of the expected behavior of the system you will design. 2. Draw a truth table describing the behavior of the circuit. The truth table should show the inputs: aj aobibo (in this order) and the outputs: c1Co · 3. Write the canonical SOP…

parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.