3. Assume a non-pipelined processor takes 100ns to process an instruction. The sameinstruction can be executed in a 5-stage pipelined processor, where each stage takes 20 ns. (i) What is the minimum number of instructions for which the speedup achieved by the pipelined processor (compared to the non-pipelined processor) is at least 4? (ii) The instruction takes the same time (100 ns) to execute whether on the pipelined processor or on the non-pipelined processor. So why do we say pipelining speeds up execution?

3. Assume a non-pipelined processor takes 100ns to process an instruction. The sameinstruction can be executed in a 5-stage pipelined processor, where each stage takes 20 ns. (i) What is the minimum number of instructions for which the speedup achieved by the pipelined processor (compared to the non-pipelined processor) is at least 4? (ii) The instruction takes the same time (100 ns) to execute whether on the pipelined processor or on the non-pipelined processor. So why do we say pipelining speeds up execution?

Name: 3. Answer the question 3. Assume a non-pipelined processor takes 100ns
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Description: 3. Answer the question 3. Assume a non-pipelined processor takes 100ns to process an instruction. The sameinstructioncan be executed in a 5-stage pipelined processor, where each stage takes 20 ns.(i) What is the minimum number of instructions for whi

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?
A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.
True/False Run times of the typical five stages to execute an instruction are as given in some units of time: Instruction Fetch: 10 Instruction Decode: 15 Execute: 30 Memory: 50 Write Back: 20 If this is implemented as a pipelined versus a non-pipelined machine, then depending on the absence of hazards, one could expect the speedup to be about 2.5.
In an unbalanced pipelined implementation, the time required to execute each individual instruction is same as for non-pipelined implementation. Select one: O True O False
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages, but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. What is the speed up achieved in this pipelined processor? 5
Suppose an instruction takes 6 cycles to execute in an unpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to determine the addressing mode of the operands, one cycle to fetch any operands, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a 6 stage pipeline, that instruction still takes 6 cycles to execute, so how can we say the pipeline speeds up the execution of the program?
In a perfectly balanced pipelined implementation, the time required to execute each individual instruction is same as for non-pipelined implementation. Select one: O True O False
In a non-pipelined processor, to execute one instruction 5 cycles are needed. The clock speed of non-pipelined processor is 4 GHz. If same processor is changed to pipelined processor having 6 stages. The clock rate of pipelined processor is changed to 3 GHz. What is the speedup achieved in this pipelined processor? (Assume no stalls in pipelined processor)
In an unbalanced pipelined implementation, the time required to execute each individual instruction is same as for non-pipelined implementation. 1true 2 false
Assume a 5-stage pipelined CPU (IF – ID – MU– EX – WR) requires following time for differentsections: Pipeline stages ----Required time Fetch Unit ---15 nsDecode Unit ---10 nsMemory Unit---- 20 nsExecution Unit---- 8 nsWrite back Unit ----15 ns The maximum delay required to transfer contents from one state to another is 2ns.a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume thatInstruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions:7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU readonly one data from RAM or save only one data to RAM at a time. Calculate the execution timefor the first 10 instructions of a program as well. Assume the condition is evaluated TRUE.
3. A non-pipelined processor has a clock rate of 2.5GHZand an average CPI of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to2GHz. 3.1 What is the speedup achieved for a typical program? Assume that it consists of 100 instructions. The speedup is the ratio between the two processors in terms of the time required to execute the program. 3.2 What is the MIPS rate for each processor? In case of the pipelined processor, ignore the initial filling up.
) A 32-microprocessor executes the instruction in unequal five-stage instruction pipeline: FI=2ms, DI=2.5ms, CO=3ms, FO=2ms, EI=1.5ms. Draw the timing diagram for instruction pipeline operation for 10 instructions program when conditional jump take place from instruction 3 to instruction 8. Mention the time duration of each stage in pipeline diagram.