2. Design a three-bit counter like circuit controlled by the input w. If w = 0, then the counter subtracts 2 from its contents, wrapping around if the count reaches 0 or 1. Thus if the present state is 1 or 0, then the next state becomes 7 or 6, respectively. If w = 1, then the counter adds 2 to its contents, wrapping around if the count reaches 6 or 7. Thus if the present state is 6 or 7, then the next state becomes 0 or 1, respectively. Use positive edge triggered T Flip-Flops without Reset input. Show all the design steps. Write the Verilog code according to your design and simulate.

2. Design a three-bit counter like circuit controlled by the input w. If w = 0, then the counter subtracts 2 from its contents, wrapping around if the count reaches 0 or 1. Thus if the present state is 1 or 0, then the next state becomes 7 or 6, respectively. If w = 1, then the counter adds 2 to its contents, wrapping around if the count reaches 6 or 7. Thus if the present state is 6 or 7, then the next state becomes 0 or 1, respectively. Use positive edge triggered T Flip-Flops without Reset input. Show all the design steps. Write the Verilog code according to your design and simulate.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 9VE

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