Design a two-bit counter (sequential circuit) using falling edge triggered T-flipflops, with one input line x. When x = 1, the state of the circuit remains the same. When x = 0, the circuit goes through the state transitions by incrementing the state count, i.e., from 00 to 01, 01 to 10, 10 to 11, and 11 to 00, and repeats. Draw circuit diagram

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Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
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Chapter1: Introduction
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Design a two-bit counter (sequential circuit) using falling edge triggered T-flipflops, with one input line x. When x
= 1, the state of the circuit remains the same. When x = 0, the circuit goes through the state transitions by
incrementing the state count, i.e., from 00 to 01, 01 to 10, 10 to 11, and 11 to 00, and repeats. Draw circuit diagram
of the designed counter. if z=83,Convert z to Base-2, e.g., z= (156)10 = (10011100)2.
Provide this bitstream as input to K and draw the timing diagram of the outputs of both the T-flipflops.

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