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- Q2/A) Design 8x1 multiplexer using 2x1 multiplexer? Q2 B)Simplify the Logic circuit shown below using K-map then draw the Simplified circuit? Q2/C) design logic block diagram for adding 12 to 5 using full adder showing the input for each adder?logic circuit diagram for fabinaaci counter that gives output in fabinaaci sequence.upto 2 digits please mentions the gates and ics used in circuit.Design Master-Slave Flip Flop circuit diagram and write a short description.
- d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.(a) Study the sequential circuit constructed by two D FFs with an active-high synchronous reset in Figure 2.1 X D Q D CLK R R Figure 2.1: Sequential circuits with two D-FFs and an AND gate Copy and complete the following timing diagram. You may ignore propagation delays in the logic gates and flip-flops. CLK X 1What’s the difference between sequential and combinational circuits? Also explain what’s the difference between positive and negative edge clock inputs for the flip-clops.
- Design a combinational circuit using multiplexer for a car chime based on thefollowing system: A car chime or bell will sound if the output of the logic circuit(X) is set to a logic ‘1’. The chime is to be sounded for either of the followingconditions:• if the headlights are left on when the engine is turned off and• if the engine is off and the key is in the ignition when the door is opened.Use the following input names and nomenclature in the design process:• ‘E’ – Engine. ‘1’ if the engine is ON and ‘0’ if the engine is OFF• ‘L’ – Lights. ‘1’ if the lights are ON and ‘0’ if the lights are OFF• ‘K’ – Key. ‘1’ if the key is in the ignition and ‘0’ if the key is not in the ignition• ‘D’ – Door. ‘1’ the door is open and ‘0’ if the door is closed• ‘X’ – Output to Chime. ‘1’ is chime is ON and ‘0’ if chime is OFF(a) Consider the flipflop circuits below: (i) Name the 2 circuits given in the figure. Explain how they are different from each other. a. b. (ii) Choose from the list the input that triggers data to travel to the next flipflop in a counter. A: Input at top NAND gate B: Input at bottom NAND gate C: Clock input clk QA certain digital circuits designed to operate with voltage levels of -0.2Vdc and -3.0Vdc. If H= 1 =-0.2 Vdc and L =0 =-3.0 Vdc, is this positive logic or negative logic ? H=+5.0Vdc. and. L=+1.0Vdc What are the voltage levels between fall and rise times are measured? What is the value of Duty cycle H if the waveform is high for 2 ms and low for 5 ms?
- Electrical Engineering 3. For the logic circuit in Figure 1, compute the following parameters: A) The total number of single stuck-at faults. B) The total number of all possible multiple stuck-at fault combinations. C) The total number of stuck-open faults. Note: You can assume that 3-input AND gate is realized using 8 transistors, a two-input OR gate is realized using 6 transistors, and an inverter is realized using 2 transistors.(a). If I want to store 4-bit data 0110 and at 4th clock I want to extract all the stored bits, which shift register I should explain it with the help of circuit diagram and table. (b). Write comparison between Diode transistor logic and Transistor Transistor logicF4 Using two flip-flops and basic gates, construct the circuit of the given state diagram below. Provide the following: State Table, Flip-flop equations, Circuit Diagram. Follow correct label names: Q0, Q1 – prev/present states D0, D1 – D-FF names X – input Y - output