1. How many states are there in an 8-bit Johnson counter sequence? 2. Write the sequence of states for a 3-bit Johnson counter starting with 000.
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Q: 1. How many states are there in an 8-bit Johnson counter sequence?
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- Below is a 4-bit up-counter. What is the largest number of the counter if the initial state Q 3 Q 2 Q1Q0 =0011? (D 3 an Q 3 are MSB, and when Load = 1 and Count =1 the counter is loaded with the value D 3 ...D0) 4-bit counter Clock Q3 Load Count "I" or Vcc "I" or Vcc Do "1" or Vcc - D, Qi Q2 "0" or Gnd - D2 "0" or Gnd D3 Q3 1111 0011 1100 0110In this part you will construct a 1G x 8 RAM Chip using both a row and column decoders. Assume that the RAM cells are organized in a 2-dimensional array so as to require the least number of gates in the two decoders. What are the dimensions of the array? What is the size of the row decoder? What is the size of the column decoder? Compute the ratio of the number of AND gates needed with this design and the number of AND gates needed for a design with only one decoder. Express your answer in powers of 2.Computer M has 8-bit memory width with 8-bit address as illustrated in Figure Memory Memory Address 1 3 -8-bit width Figure . A 32-bit data, AIB2C3D4 is going to be stored in the memory. Illustrate the content of the memory if the data being stored using: (a) Big Endian (b) Little Endian
- Solve the problem and simplify the output function using Quine–Mc Cluskey Methods. The following requirements must be met in solving the problem. Requirement:a. Truth Tableb. Timing Diagramc. Quine – Mc Cluskey Method d. Logic Diagram A private company wants to decide on a certain issue. Each of the four officials has an equal share of voting right. At least two of them must approve the solution in order to implement it. Each of them has a switch which closes to vote YES and open to vote NO.1. Assume that the registers are 8-bit wide. Consider the following code: MOV R1, #4A MOV R2, #40 ADD R3, R1, R2 a) What will be the 8-bit result in Register R3 (in hex)? b) What is the 8-bit result in Register R3 (as unsigned decimal)? c) What is the 8-bit result in Register R3 (as signed decimal)? d) What will be the value of the carry (C) bit?A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWNmode is (a) 0001 (b) 1111 (c) 1000 (d) 1110
- -The operation of the instruction MOV CS, CX is O not allowed. O copies CX into CS. copies the content of memory location into CX. O copies CS into CX.Construct a 4-bit Johnson counter using J-K flip-flops. (See Figure 12-12 for a Johnson counter.) What sequence of states does the counter go through if it is started in state 0000? State 0110?4- a) What are the main applications of the comparator? b) Design two two bit comparator. 5- Convert five bit Gray to binary code, write truth table and draw the circuit diagram. 2-5
- Task 6: Simplifying Boolean functions in EWB using the logic converter Simplify the following Boolean expression in EWB using the logic converter F (A, B, C) = AB'C'+ A'B'C'+ A'BC'+ A'B'CCreate a circuit to generate odd parity bit for a 3-bit code. a. Construct the truth table. b. Use K-map to simplify the circuit. c. Draw the circuit with minimum number of gates. (I did the question myself, but I'm confused as to why the K-map does not provide the simplified circuit to build the minimum number of gates)Computer architecture 1- A digital computer has a memory unit with 64 bits per word and 256G memory. The instruction set consists of 532 different operations. All instructions have an opcode, general register, index register, mode, future and address fields. This particular system includes 32 general- purpose registers, 8 index register,4 modes, future and address. a) How many bits are needed for the opcode? b) How many bits are needed to specify the general and index registers? c) How many bits are needed to specify the mode and the future? d) How many bits are needed to specify the address? e) What is the largest unsigned binary number that can be