Programmable Logic Controllers
5th Edition
ISBN: 9780073373843
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
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Expert Solution & Answer
Chapter 8, Problem 2P
Explanation of Solution
a.
Status of output B3:0/9:
- Here, the input will be activated when the input push button is pressed down.
- A temporary signal will be provided by “B3:0/1” which will be resided for some time; this will generate the off-to-on transition signals...
Explanation of Solution
b.
Status of output B3:0/9:
- Here, the trigger signal will be turned OFF when the input push button is released; which makes “B3:0/1” to remain OFF.
- Here, the output “B3:0/9” is also in OFF state until the trigger is in the OFF state...
Expert Solution & Answer
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Students have asked these similar questions
2. Design a logic circuit with two inputs and 4 outputs, with each of the outputs hooked up to an LED. Only the first LED should light up
when the input values are 00. Only the next LED should light up with the input values are 01. Only the following LED should light up for
10, and only the last LED should light up for input 11. Thus for each input combination, you should have one LED only being lit. This is
called a DECODER circuit, you are decoding 2 bit binary input to one of 4 discrete outputs.
a. Create the truth table (use the standard truth table format).
b. Write a Boolean expression that corresponds to the truth table.
Design a combinational circuit with four inputs— A, B, C, and D —and one output, F . F is to be equal to 1when A = 1, provided that B = 0, or when B = 1, provided that either C or D is also equal to 1. Otherwise,the output is to be equal to 0.1. Obtain the truth table of the circuit.2. Simplify the output function.3. Draw the logic diagram of the circuit, using NAND gates with a minimum number of ICs.4. Construct the circuit and test it for proper operation by verifying the given conditions.
2. Design a logic circuit that controls an elevator door in a three-story building. The circuit has four inputs.
M is a logic signal that indicates when an elevator is moving (M=1) or stopped (M=0). F1, F2 and F3
are floor indicator signals that are normally LOW, and they go HIGH only when the elevator is
positioned at the level of that particular floor. For example, when the elevator is lined up level with
the second floor, F2=1 and F1=F3=0. The circuit output is the OPEN signal which is normally LOW
and is to go HIGH when the elevator door is to be opened.
Chapter 8 Solutions
Programmable Logic Controllers
Ch. 8 - Name the three forms of PLC counter instructions,...Ch. 8 - State four pieces of information usually...Ch. 8 - In a PLC counter instruction, what rule applies to...Ch. 8 - Prob. 4RQCh. 8 - When does the PLC counter instruction increment or...Ch. 8 - Prob. 6RQCh. 8 - Prob. 7RQCh. 8 - Prob. 8RQCh. 8 - Prob. 9RQCh. 8 - Prob. 10RQ
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Similar questions
- 3. Design a logic circuit that controls an elevator door in a three-story building. M is a logic signal that indicates when the elevator is moving (M = 1) or stopped (M = 0). F1, F2, and F3 are floor indicator signals that are normally LOW, and they go HIGH only when the elevator is positioned at the level of that particular floor. For example, when the elevator is lined up level with the second floor, F2 = 1 and F1 = F3 = 0. The circuit output is the OPEN signal, which is normally LOW and will go HIGH when the elevator door is to be opened. We can fill in the truth table for the OPEN output as follows: a. Because the elevator cannot be lined up with more than one floor at a time, only one of the floor inputs can be HIGH at any given time. This means that all those cases in the truth table where more than one floor input is a 1 are don't-care conditions. We can place an x in the OPEN output column for those eight cases where more than one F input is 1. b. Looking at the other eight…arrow_forwardTRUE or FALSE 11. In a Boolean equation the use of the + symbol represents the OR function. 12. A logic gate has one or more output terminals and one input terminal. 13. An inverter output is the complement of its input. 14. It is important to memorize logic symbols, Boolean equations, and truth tables for logic gates.arrow_forward• Design a sequential circuit with two T Flip Flops, A and B, and two inputs, E and x. If E=0, the circuit remains in the same state regardless of the value of x. When E=1 and x=1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. When E=1 and x=0, the circuit goes through the state transition from 00 to 11 to 10 to 01 back to 00, and repeatsarrow_forward
- 1. Design the state diagram and create the state table for a synchronous to detect the sequence 0101. The circuit has a single input, x, and a single output z. The output is logic-1 whenever the input sequence 0101 is detected, logic-0 otherwise. Note that overlapping sequences are allowed (that is: If the input is 01010101, the output is high on every 1 beginning with the second). Write the equations for the state variables and the output z ?arrow_forwardQ3: A majority circuit is a combinational circuit whose output is equal to 1 if the input variables have more 1's than 0's. The output is 0 otherwise. Answer 3 of the following questions: A- Design a 3-input majority circuit by finding the circuit's truth table, Boolean equation, and a logic diagram? B- Program and determine how many Configurable logic block (CLB) you wouid need for such circuit in Part A to be implemented in the FPGA then program this FPGA to emulate 3-input majority if you know that the CLB structure are: Look-Up Table (LUT) MUX A+B-t OLR C- Redesign the logic circuit of Part A using universal logic gate NOR?arrow_forwardödaly čbäi A combinational logic circuit has one output (F) and four inputs (a, b, c, and d). The circuit is described by the following Boolean expression. To remove the static one hazard, the designer should add the term(s) to F ..... ..... abd and abc' O a'bc' and ab'd' O a'b'd' and a'b'c' O abd a'bc' and a'b'd' ab'd acd Oarrow_forward
- Which of the following is true for the two verilog codes given? 1. Behavioral design level is used. II. Output(y) is equal to logic 1 and the text "y-logic 0" appears in the simulation. III. The combinational circuit designed in the code includes 3 logic gates. IV. A net has to be added to the code for the output. `timescale lns / lps module mainfunction (input a, b, c, output y); assign y=(a&b) | (alc); endmodule timescale ins/lps module testbench; reg a,b,c; mainfunction dt (.a (a),.b (b), .c (c),.y(y)); initial begin a=0; b=0; c=0; #10 if (y!==1) $display("y-logic 0"); end endmodulearrow_forwardنقطة واحدة A combinational logic circuit has one output (F) and four inputs (a, b, c, and d). The circuit is described by the following Boolean expression. To remove the static one hazard, the designer should * .add the term(s) . . to F acd O a'b'd' and a'b'c' O abd a'bc' and ab'd' O abd and abc' O a'bc' and a'b'd' ab'd Oarrow_forwardA5. Examine the logic circuit in Fig. 5.2, and write the Boolean expression for output G. A7. Construct the K-map to simplify G. G= CD 00 01 11 10 AB 00 01 11 10 A8. Write the Boolean expression of G by using the K-map. G= D A9. Draw the logic diagram of the simplified expression in the space provided below. Fig. 5.2 A6. Connect the circuit as shown in Fig. 5.2, set binary switches to each set of input values and record the corresponding outputs in Table 5.2. Table 5.2 A В D G A10. Construct the simplified expression by using only NAND gates. Design and draw the NAND gates connection diagram of simplified function 1 1 1 1 1 1 A11. Construct the circuit diagram obtained in A10 and set binary switches to each set of input values as in Table 5.2. 1 1 Does the circuit constructed in A10 give the same outputs of circuit in Fig. 5.2? 1 1 1 1 1 1 1 1 1 1 1arrow_forward
- C1. Consider the designing of a synchronous circuit to detect the sequence 0110. The circuit has a single input x, and a single output z. The output is logic-l whenever the input sequence 0110 is detected, logic-0 otherwise. Note that overlapping sequences are allowed. Answer the following questions: a. Complete the following state diagram of the circuit: 1 so s1 S2 S3 S4 b. Draw and fill the state table of the circuit. c. Write the equations of the state variables and the output Z.arrow_forwardComputer Science 1. Design a circuit for a digital lock using the minimum number of D latches. The lock has two input push-button switches A, B and it outputs a single pulse (Z1) for each activation i.e. lock open. The two switches are interlocked mechanically so that simultaneous pulses are not possible. The lock should have the following features: a. The opening sequence is 0011. ii. Then replace ‘0’ by ‘A’ and ‘1’ by ‘B’ in the sequence. b. Five B pulses should give an absolute reset. c. Any incorrect use of the A switch will cause an output (Z2) to ring a bell to warn that the lock is being tampered.arrow_forwardQ2): Design a sequential circuit with two T flip-flops A and B, and one input x_in. (a) When x_in = 0, the state of the circuit remains the same. Whenx_in = 1, the circuit goes through the state transitions from 00 to 01, to 11, to 10, back to 00, and repeats. (b) When x_in= 0, the state of the circuit remains the same. When x_in=1, the circuit goes through the state transitions from 00 to 11, to 01, to 10, back to 00, and repeats.arrow_forward
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