Computer Organization and Design MIPS Edition, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)
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Chapter 6, Problem 6.19.2E
Program Plan Intro

Given Information:

It is given that there are three classes of CPU:

CPU A: it is a moderate speed multi-core CPU having a floating point unit which can execute multiple instructions per cycle.

CPU B: it is a fast single-core integer CPU without any floating point unit which can execute a single instruction per cycle.

CPU C: It is a slow vector CPU with floating point capability which can execute multiple copies of the same instruction per cycle.

There are two matrices X and Y that each contains 1024 × 1024 floating point elements.

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