Programmable Logic Controllers
5th Edition
ISBN: 9780073373843
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
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Question
Chapter 10, Problem 2P
Program Plan Intro
Counter:
- Counter is a device used to store a particular event has occurred various number of times.
- There are two types of counter namely,
- Down counters
- Down counters are already set with some value.
- It counts downwards from that value to zero.
- When it reaches zero, it achieves change state.
- Up counters
- Up counters counts upwards from zero to some preset value.
- When it reaches the preset value, it achieves change state.
- Down counters
Explanation of Solution
b.
Steps to operate the program to set Pilot Light 1 (PL1) output to βONβ:
- Press the reset Push Button (PB) to reset the counter to zero.
- To make a count of off-to-on transitions to 25, set the thumbwheel switch to a count of 025...
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you need to design and draw a 3-bit synchronous binary up/down counter for experiment 5. You need to add a bit named "M" for the excitation table that helps it switch between up and down mode and draw the state transition diagram, excitation table, k-map and circuit diagram with T-flip flops. When M = 0, it will perform up
counter. When M = 1, it will perform down counter.
11. Implement the given function f(A,B,C,D)=[(0,1,3,4,8,9,15)using 8:1 Multiplexer.
12. a. Design a control enabled JK FLIPFLOP using appropriate number of NAND gates.
b.Determine the output of the given Positive edge triggered Flip flop .Assume the previous
value of Q to be 0. Draw the output for the positions numbered from 1 to 5 at Q.
CLK
R
2
Write a Verilog code with testbench for 16-bit up/down counter with
synchronous reset and synchronous up/down.
If up/down is set the counter is up counter and if it is not set, the
counter is a down counter.
clock
reset
Up/down
submit the module code, testbench code, and the simulation results.
Chapter 10 Solutions
Programmable Logic Controllers
Ch. 10 - In general, what do data manipulation instructions...Ch. 10 - Prob. 2RQCh. 10 - Prob. 3RQCh. 10 - Prob. 4RQCh. 10 - Prob. 5RQCh. 10 - Prob. 6RQCh. 10 - Prob. 7RQCh. 10 - Prob. 8RQCh. 10 - Prob. 9RQCh. 10 - Prob. 10RQ
Ch. 10 - Prob. 11RQCh. 10 - Prob. 12RQCh. 10 - Prob. 13RQCh. 10 - Prob. 14RQCh. 10 - Prob. 15RQCh. 10 - Prob. 16RQCh. 10 - Prob. 17RQCh. 10 - Prob. 18RQCh. 10 - Prob. 19RQCh. 10 - Prob. 20RQCh. 10 - Prob. 21RQCh. 10 - Prob. 22RQCh. 10 - Prob. 1PCh. 10 - Prob. 2PCh. 10 - Prob. 3PCh. 10 - Prob. 4PCh. 10 - Prob. 7PCh. 10 - Prob. 8PCh. 10 - Prob. 9PCh. 10 - Prob. 10PCh. 10 - Write a program that will cause a light to come on...Ch. 10 - Write a program that will cause a light to come on...
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- Problem 2: You are to design and simulate a sequential circuit which has two inputs, X and an enable input, E. You will be using two JK Flip-Flops in your design. The following is the requirements for your design: When the circuit is disabled, i.e., E = 0: There will be no change, that is, the circuit remains in the same state regardless of the value of X. When the circuit is enabled, i.e., = 1: If X = 1, the circuit goes through circular state transitions, 00 > 01 β 10 β 11 β 00 and repeats, If X = 0, the circuit goes through circular state transitions, 00 > 11 β 10 β 01 β 00 and repeats,arrow_forwardAssuming that a certain ASM chart has 2 states, what is the minimum number of flip flops required to implement it using the sequence register and decoder approach: Select one: a. None of the given b.2. Ρ 3 d. 1 Question 2.. In the following code, what is the value of the output if the input is 111 module circuit (A, B, C, D, E) output D, E input A,B,C wire w or X3 (D, W. E): not X2 (EC) and X1 (M.A, A); endmodule Select one a. D-0, E-1. E, D=0, E=0. C. ex. out=x. d. D-1, E-1. e. D=1, E=D.arrow_forward2. The process of adressing each input during one clock pulse is calledarrow_forward
- Write a Verilog code with testbench for 16-bit up/down counter with synchronous reset and synchronous up/down. If up/down is set the counter is up counter and if it is not set, the counter is a down counter submit the module code, testbench code, and the simulation results.arrow_forwardonly one of the following statements is false according to the Sequential circuit. a. it contains at least one memory element b. it can contain multiple combinational circuit c. The output states depend on present states d. All inputs and outputs are applied at the same timearrow_forwardYour task is to implement the ALU using Hardware Description Language (HDL).Your first step will likely be to create a logiccircuit that manipulates a 16-bit input accordingto the nx and zx control bits (i.e., the circuitshould conditionally zero and negate the 16-bitinput). This logic can be used to manipulate thex and y inputs, as well as the out output. By thispoint in the unit, you would have already builtthe chips for bitwise And-ing and addition. Thus,what remains is to build logic that choosesbetween them according to the f control bit.Finally, you will need to build logic thatintegrates all the other chips into the overallALU.arrow_forward
- Ex4: Design a counter with 7 flip-flops that goes through the following binary repeated sequence: 0, 1, 3, 7, 6, 4. Show that when binary states 010 and 101 are considered as don't care conditions, the counter may not operate properly. Find a way to correct the design with don't care and without don't care The number of flip-flops required is three. β’ Table below shows the desired circuit excitation table. Present Next Flip-flop inputs state state ABC ABC TA TB C 000 001 0 0 1 001 011 0 1 0 010 XXX X X X 011 111 1 1 0 100 000 1 1 0 101 XXX X X X 110 100 0 1 0 111 110 0 0 1arrow_forwardQ1: Answer the Questions as Directed : a. Identify with proper name and Draw the circuit diagram of a latch/Flip flop that is represented by the given truth table AB Q Q+ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Inputs not allowed b. Construct the Latch/Flip Flop identified in section Q1a in Multisim software and attach the output with your name on top of screen shot here c. What is the major difference between SR Flip Flop and JK Flip Flop ?Support your answers with Logic diagram and truth table d. Write conclusion based on your simulation of the Latch/Flip flop in Q1a.arrow_forwardDesign a 3-bit counter that starts at 7 and decreases by 2 until it reaches 1. Once it reaches 1 the counter returns to 7 and continues counting in the same manner. Additionally, it must be implemented using T-flipflops, and your answer must include: The state graph (be detailed and contain all proper directions, labels, and values) The truth tables (needs to include the truth table for the next state and truth table for the logic for the flip flops) The K-maps for the next state equation and the K-maps for the logic gates connected to the flip flops Determine the optimal SoP next state equations and the optimal SoP equations for the logic gate(s) connected to the flip flops Lastly, draw the digital circuit of the control unit all the way to the outputs that will be connected to the conveyor belt.arrow_forward
- USE LOGISM TO COMPLETE THE FOLLOWING AND SHOW ANSWER IN LOGISM VIA IMAGE/SCREENSHOT Β The most important and possible most difficult component to implement is the arithmetic logic unit. Thefunctions of the ALU are shown in Table 1. The ALU should have 5 inputs (A-input, B-input, F0-input, F1-input, Finput) and 1 output (C-output). You will need to determine how many bits each input and output should have.Remember, you are designing an 8-bit microprocessor! To achieve the specified ALU functions, think aboutwhich digital logic component(s) you can use to accomplish the task. For example, to add the value on the A-bus8-bit ALUD3D2D1D0A BF0F1F2C0=0, C1=0C0=0, C1=1C0=1, C1=0C0=1, C1=1 B0=1, B1=1B0=1, B1=0B0=0, B1=1C2to the value on the B-bus, you can simply use an 8-bit adder. Explore the components in Logisim! Additionally,you can think about using a multiplexer to determine which ALU function will be performed.arrow_forwardElectrical Engineering 6. For the state diagram below, determine the D flip-flop input expressions for an implementation using one-hot encoding. Assume the notation for the flip-flop inputs and outputs follows that of DA and QA, respectively. For example, DA, DB , ... and QA, QB . Also provide an expression for the output F. X-D0 X=0- X-1- A/0 B/0 X=0 X-1 C/1arrow_forwardWith the aid of Table-1 in the back of this exam paper, answer the following: a- Design the control signal and for the memory write operation. b- Draw the logic diagram of the control signal derived in (a).arrow_forward
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