Programmable Logic Controllers
5th Edition
ISBN: 9780073373843
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
expand_more
expand_more
format_list_bulleted
Concept explainers
Question
Chapter 10, Problem 13RQ
Program Plan Intro
Data comparison instructions:
- Data comparison instructions refer to input instructions.
- It is used to compare two numerical data values and take decisions based on the program instructions.
- It can also be used to check the numerical value pairs for determining if a rung is true.
- The basic set of data comparison functions performed by PLCs are as follows:
- Equal to (=)
- Not equal to (!=)
- Less than (<)
- Greater than (>)
- Less than or equal to(<=)
- Greater than or equal to (>=)
- The above given compare instructions are used to compare the values of source A and source B.
Terms used:
The following terms are used in the instruction.
- Source A
- Source A refers to the address of the first piece of data that is used in the instruction.
- Source B:
- Source B refers to the address of the second piece of data that is used in the instruction.
Explanation of Solution
b.
LESS THAN instruction:
- The LESS THAN (LES) instruction is used to test whether the given value is less than the other value or not.
- If the given value such as Source A is less than Source B, then the instruction is logically true. Otherwise, the given instruction is logically false.
Explanation:
In the given logic rung,
- The output D is energized whenever input C is true...
Explanation of Solution
c.
GREATER THAN OR EQUAL instruction:
- The GREATER THAN OR EQUAL (GEQ) instruction is used to test whether the given value is greater than or equal to the other value or not.
- If the given value such as Source A is greater than or equal to Source B, then the instruction is logically true. Otherwise, the given instruction is logically false.
Explanation:
In the given logic rung,
- The output F is energized whenever input E is true...
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solutionStudents have asked these similar questions
Q3: Design an asynchronous counter that divides the input clock signal by 5 then draw
counter's logic circuit and its corresponding timing diagram for 10 clock pulses.
Duar
With the aid of Table-1 in the back of this exam paper, answer the following:
a- Design the control signal and for the memory write operation.
b- Draw the logic diagram of the control signal derived in (a).
: Based on the logic circuit given in Figure 1. Design a shift register that displayed
the input data on its output after 32 us. You can use any extra logic components
when necessary.
Data In
Q7 (Data Out)
SRG 8
Clock
Q7
500 kHz
Figure 1: Logic circuit for serial-in / serial-out shift register
Chapter 10 Solutions
Programmable Logic Controllers
Ch. 10 - In general, what do data manipulation instructions...Ch. 10 - Prob. 2RQCh. 10 - Prob. 3RQCh. 10 - Prob. 4RQCh. 10 - Prob. 5RQCh. 10 - Prob. 6RQCh. 10 - Prob. 7RQCh. 10 - Prob. 8RQCh. 10 - Prob. 9RQCh. 10 - Prob. 10RQ
Ch. 10 - Prob. 11RQCh. 10 - Prob. 12RQCh. 10 - Prob. 13RQCh. 10 - Prob. 14RQCh. 10 - Prob. 15RQCh. 10 - Prob. 16RQCh. 10 - Prob. 17RQCh. 10 - Prob. 18RQCh. 10 - Prob. 19RQCh. 10 - Prob. 20RQCh. 10 - Prob. 21RQCh. 10 - Prob. 22RQCh. 10 - Prob. 1PCh. 10 - Prob. 2PCh. 10 - Prob. 3PCh. 10 - Prob. 4PCh. 10 - Prob. 7PCh. 10 - Prob. 8PCh. 10 - Prob. 9PCh. 10 - Prob. 10PCh. 10 - Write a program that will cause a light to come on...Ch. 10 - Write a program that will cause a light to come on...
Knowledge Booster
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.Similar questions
- Design a CMOS circuit to implement the logic function. The design should not include a CMOS inverter at the output. Y = ABC+ABC + ABCarrow_forwardDesign a three-bit up/down counter using T flip-flops. It should include a control input called Up/Down. If Up/Down = 0, then the circuit should behave as an up-counter. If Up/Down = 1, then the circuit should behave as a down-counter.arrow_forward"What are the three basic logic operation and differentiate each operation?"arrow_forward
- 6. The state diagram for a sequential circuit appears in the following figure. X,X2/Z_00/0,11/0 01/0, 10/1 B 00/0,01/0 A Reset 00/1,01/0 01/1, 10/0 10/1, 11/1 00/1, 11/1 D 10/1, 11/0 (a) Find the state table for the circuit, (b) Find an optimized circuit implementation using T Flip-Flops, NAND gates, and inverters.arrow_forwardDesign a 9v DC oscillator circuit that produces a frequency of 500 Hz. The circuit may use a 555 timer or two transistor design(s). Show all calculations including the DC currents and bias voltages. Include the schematic and the required frequency formula(s). Do the best you can as the process to arrive at a final answer will be evaluated as well. From this, if a larger load were required to be connected to the chip, how would the schematic look and what components would be used to do design it? Also, as a theoretical approximation, if the 9v battery had a rating of 4 amp-hours, how long would it last powering this circuit? Show calculations to illustrate how you arrived at the answer. Remember, these questions are a reflection of your own work. Make sure any references used are cited.arrow_forward2. Consider the following operation: Z = AB • BC a) Write out the truth table for the given expression. b) Design a logic circuit that implements the given expression using 6 NMOS devices only. Draw the logic gates diagram first. Use 2-input logic gates only. No need to indicate values for the supply voltage and pull-up resistors. (Hint: You need to manipulate and rewrite the expression using DeMorgan's Theorem) c) Given a supply voltage of 5V and assuming low states to be OV, redraw the equivalent circuit and label all important voltages when A = 5V, B = 5V, and C = 5V.arrow_forward
- Q1 a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.) Part DigClock Part List: OFFTIME = .5uS DSTM1 ONTIME = .5us DELAY = STARTVAL = 0 OPPVAL = 1 DisClock FileStm1 FieStm16 CLK FileStim2 FileStim32 FileStim4 FileStime Libraries Design Cache EVAL 1. SOURCEarrow_forwardConstruct a logic circuit on the ROM that produces the outputs given in the table below by comparing the two bits and two magnitudes applied to its input. Show the design clearly (ROM sizes, ROM data table).arrow_forwardDraw the timing diagram of the outputs QO, Q1, Q2, Q3 showing the operation of the sliding circuit. Bi-directional register as shown in Figure 3, corresponding to the control signal. RIGHT/LEFT and signal The defined CLK clock is shown in Figure 4. The circuit has initial states Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 1 and has input data equal to 0arrow_forward
- 17. Determine the output expression of the LUT for the internal conditions shown in Figure 10-72 Selection logic Memory cells 1 A 3 B SOP output 5 1 7 FIGURE 10-72 - 2.arrow_forward1. Design a simple logic circuit for a Set/Reset (SR) Latch, based on any actual application of latches. 2.) Describe your design using at least three (4) sentences. Note: Look at the example guide on the image.arrow_forwardDraw a logic diagram of a four-bit register with four D flip-flops and four 4x1 multiplexers with mode selection inputs for S1 and SO. The register operates according to the following function table. S1 So Register Operation No change 1 Complement the four outputs 1 Clear the register to 0 (synchronous with clock) 1 1 Load parallel data Yükle Bir Dosya Seçinarrow_forward
arrow_back_ios
SEE MORE QUESTIONS
arrow_forward_ios
Recommended textbooks for you
- Systems ArchitectureComputer ScienceISBN:9781305080195Author:Stephen D. BurdPublisher:Cengage Learning
Systems Architecture
Computer Science
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Cengage Learning