Write VHDL code for a Laser Circuit FSM that shows separate “blocks” for the next state decoder, memory, and output decoder. Add an Asynchronous Reset active Low

Given: In a Laser Circuit FSM, the output x equals 25 nanoseconds, and Tclk equals 5 nanoseconds. Question: Write VHDL code showing separate “blocks” for the next state decoder, memory, and output decoder. Add an Asynchronous Reset active Low.

Plot the sine wave at frequency fm and the sampling signal at frequency fs1. Write a MATLAB program to take input both fm and fs1 and plot the curves mentioned above.

you need to design and draw a 3-bit synchronous binary up/down counter for experiment 5. You need to add a bit named "M" for the excitation table that helps it switch between up and down mode and draw the state transition diagram, excitation table, k-map and circuit diagram with T-flip flops. When M = 0, it will perform up counter. When M = 1, it will perform down counter.

In verilog a counter must be developed from 0 to 9999 with a reset and parallel loading. The reset will be a button in charge of returning the count to 0 when pressed.For this practice, the implemented circuit will only use a 7-segment BCD converter module, which will have to be managed between the different 7-segment displays at a given frequency.

Build the monostable 555 circuit on TinkerCAD, where the output is an LED.

Design and implement using T-FF a synchronous loop counter that counts: 5>3>0>1>6 and back to 5 in a loop. Use the Tina software to implement the circuit of the counter.

build a full adder circuit with I/O switched on input wires, LEDs on output and naming input and output wires properly