Write synthesizable VHDL code for a 5-to-10 decoder with an enable signal, active low, and outputs active low

Write VHDL code for this FSM. Add an asynchronous RESET, active High to the state diagram.

Write a VHDL code to implement a shifter which shift right 4 bits of information.

Given: In a Laser Circuit FSM, the output x equals 25 nanoseconds, and Tclk equals 5 nanoseconds. Question: Write VHDL code showing separate “blocks” for the next state decoder, memory, and output decoder. Add an Asynchronous Reset active Low.