What is the pipeline and non-pipeline processor clock cycle time?

Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?

Given the following latencies-- I-Mem: 200ps, Add: 70ps, Mux: 20ps, ALU: 90ps, Regs: 90ps, D-Mem: 250ps, Sign-Extend: 15ps, Shift-Left-2: 10ps. If the only thing we need to do in a processor is fetch consecutive instructions, what would the cycle time be?

How does pipelining impact the overall instruction execution time, and what is meant by pipeline efficiency?