In the face of pipeline stalls or hazards, how do modern processors utilize idle cycles for improved efficiency?

Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?

Compilers and assemblers may sequence assembly language instructions to minimise pipeline risk. Pipeline design seeks this. Do all assemblers and compilers rearrange assembly language instructions to maximise productivity?

• If we added a new instruction format to MIPS that only specified one register, how large a constant could it hold? Briefly Explain why.