What is the modulo of the circuit below? 2. Make a table of the count sequence. 3. A BCD counter can assume____discrete state. 4. A BCD counter can divide its input frequency by____.
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- (a). If I want to store 4-bit data 0110 and at 4th clock I want to extract all the stored bits, which shift register I should explain it with the help of circuit diagram and table. (b). Write comparison between Diode transistor logic and Transistor Transistor logicparity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.please show work included 4. If a 6-bit binary number is used to represent an analog value in the range from -63 to 126, what is the accuracy of the system? In other words, if the binary number is incremented by one, how much change does it represent in the analog value?
- d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.1What will be the state of a MOD64 counter after 90 input pulses if the starting state=000000?A.100100B.011010C.010110D.011100 2.A MOD 32 counter is holding the count 101112. What will the count be after 31 clock pulses?A.10100B.10010C.10000D.10110A frequency counter is gated on for 10 ms and counts 540 pulses from a periodic input signal . What is the input frequency? a) If the gate time is changed to 100 ms , approximately how many counts would you expect from the same source during the gate time? b) In what way does the change in the gate time affect the resolution?
- a) Design Binary Ripple Counter using D-flipflop. b) Design asynchronous 4-bit UP-Down counter.Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- Cin Cout Figure Q4(a)(ii)A 9-bit asynchronous counter has a 128-kHz clock signal applied. (1) What is the MOD number of this counter? MOD number = (ii) What will be the frequency at the MSB output? fmsb = (iii) Assume that the counter starts at zero. What will be the count after 635 input pulses? After 635 input pulse, Count =
- Computer Science & Engineering Define BCD counter. A circuit consist of five cascaded BCD counters.Find the range of counting of the cascaded sequence.Q4) Design a Register File which includes four 2-bit registers (In total, it includes 8 bits). Each register is named as ala0, b1b0, c2c0, d1d0. Registers are loaded from the S input. In addition to that, there are two input signals, X and Y, to determine which register to select (ie. 00 selectsfirst register ala0 etc). Also there is R signal. When W is zero, the content of the register does not change. When the W is 1 the selected register is loaded with a new value by shifting from the S input. Design this register file by using D flip-flops.Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- B Cin Cout Figure Q4(a)(ii) (iii) Given A = 111001 and B = 100010. Construct a 6-bit parallel adder to solve for A + B.