What is the biggest drawback of a single data route architecture? Multiplexors are required because of this. The lengthiest delay determines the clock period. This platform does not support the JUMP instruction. At any one moment, each datapath element can only carry out one function.

The arrays of MISD devices are systolic. Systolic arrays are "wavefronts" or data processing component pipeline networks. These sections are self-contained and do not require programme counters, as execution is initiated by data. In systolic arrays with synchronised clocks, each CPU alternates compute and communication phases to calculate in "lockstep?

Write the corresponding Mic-2 MAL and Mic-3 instructions to implement the following IJVM assembly instructions using a minimum number of clock cycles. 1.  WORDPUSH word: Pushes an unsigned 2-byte operand to the top of the stack. 2.  BLKLOAD count : Pushes a block  of local variables onto the top of stack, starting with the first local variable. The number of variables for be pushed is specified by the 1-byte unsigned operand. 3.  INEGATE : Pops a word from the stack and push the negated value. 4.  IF_GE offset : Pop two words from stack and branch if the first popped word is greater than or equal to the second popped word.

Assume a classical RISC pipeline with regular (not delayed) branches. This pipeline has five stages: Instruction Fetch (IF), Instruction Decode (ID), Execute Instruction (EX), Memory Access (MEM), and Writeback (WB). You may assume that there are no resource hazards in this pipeline, but data hazards may exist. Draw a timing diagram that shows the execution of the following instructions in this pipeline. Assume that R1, R2, etc. are registers while A, B, etc. are memory operands. The first operand is the destination while the second operand is the source. The numbers on the left are the addresses of the instructions. BRA is an unconditional branch to a target address 120.