triggered flip-flop) for: (a) T flip-flop with active low clear (CLR') and preset (PRE') (b) T flip-flop with without a clear and preset Note: Q is initially high CLOCK CLR PRE

For a Mod 64 clocked counter we need A. 6 flip flops and 4 AND gates       B. 6 flip flops       C. None of the above       D. 6 flip flops and 2 AND gates

1) The following waveform are applied to the J-K flip flop with negative edge clock pulse. Assuming the flip flop is initially set, determine the Q output. (a) 2) Repeat question 1 for positive edge clock pulse.

For the frequency divider circuit the D-flip-flop is a CD4013 Dual D-Type flip-flop V2 is a square wave applied to the Clock input and Q is the ouput waveform. a. What is the frequency of the square wave Clock from V29? b. What is the frequency of the output pin Q? c. How many D-flip-flops are implemented in the CD4013 Chip? d. How many outputs are implemented in each D-flip-flop? List them.