The following circuit output a two-digit number, denoted as N1N2. N1 is the higher digit and N2 is the lower digit. Each block in the figure is a "up counter with parallel-load capability", as discussed in our lecture and also shown below. Which statements below correctly describe the circuit? Choose all that apply. Enable Do Qo D₁ Q1 D2 D3 2522 N₂ Q2 Q3 Load Clock Clock- Clear Enable DA Q4 D5 D6 D7 2222 Q5 N1 Q6 Q7 Load Clock Each block in the above figure is shown below. Enable Do D Q Qo D1 D Q D2 D Q D Q D3 Load- Clock Q2 Q3 Output carry This is a BCD counter. Both counters are modulo-6 counters. This is a synchronous circuit. The counter will be continuously counting as long as the Clear signal is 1.

Draw the schematic for a synchronous 3-digit up/down counter with T flip-flops, with an enable function. So there will be two control lines: En and DIR. When En = 0, the counter stops. When En = 1, the counter counts. DIR determines the counting direction. When DIR = 1, the counter counts upward. When DIR = 0, the counter counts downward. %3D

Task 5: Use NAND gates and inverters only to rebuild the circuit. a. Draw the circuit diagram below. b. Build a circuit using Multisim that is based on the above diagram and record the outputs in the columns of "Sim. O". A 0 0 1 1 B 0 1 0 1 Calculated Sim. 0₁ 0₁ Calculated 0₂ Sim. 0₂ Calculated 03 Sim. 03

The circuit below is a 4-bit shifter with 2 control inputs s1 and s0, 4 data inputs 13, 12, 11, and 10, and 4 data outputs Q3, Q2, Q1, and Q0. If the input 13 12 11 10 = 1101, what is the final output when s1 s0 = 01 and then 11 next clock cycle ? 13 12 I1 IO s1 s0 Q3 Q2 Q1 QO 0000 0010 0110 O 1010