QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)

QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

B) For a virtual memory system, the auxiliary memory was of size 8 MByte, and the number of empty entries in the memory page table was 1984. If the page and block sizes were 4 KByte, find: 1- the number of blocks in the main memory. 2- the size of main memory. 3- the number of bits in the physical address,
A virtual memory has a page size of 16 words. There are 8 pages and 4 blocks. The associative memory page table contains the following entries. (Addresses are given HEX form): Page Block a) For the following virtual addresses find the CPU addresses: 3A, 5B, 1 3 b) For the following CPU addresses find the virtual addresses: 0C, 2D 1 4
Consider a computer system with a 32-bit logical address and 4-KB page size. The system supports up to 512MB of physical memory. How many entries are there in each of the following: a) A conventional single-level page table Consider a logical address space of 256 pages with a 4-KB page size, mapped onto a physical memory of 64 frames. a) How many bits are required in the logical address? b) How many bits are required in the physical address?
I have this problem from my textbook that I do not understand, despite re-reading the section on segmentation and paging. "The IBM system/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described in Chapter 8. For the basic 370 architecture, the page size may be either 2 KB or 4 KB, and the segment size is fixed at either 64 KB or 1 MB. For the 370/XA and 370/ESA architectures, the page size is 4 KB and the segment size is 1 MB. What advantages of segmentation does this scheme lack? What is the benefit of segmentation for the 370?"Can you help me undertand what they are looking for in this explanation?
2. A memory location has a logical address where the segment address is the first four digits is your roll number and the offset address is the last four digits of your roll number. Find the physical address of the memory location. [example: if your roll number is 1234200516789, then the segment address is 1234h and the offset address is 6789h]
Exercise 1: Consider a word-addressable memory of 16 GB, where each word is composed of 128 bits. This memory is directly mapped to a cache of 1 MB composed of blocks where each block contains 16 words. a) What is length (in bits) of the address provided by the processor? b) What is the length (in Bytes) of one memory block? c) How many lines does the cache have? d) What is the length (in bits) of each of the TAG, LINE, and OFFSET? e) Which line in cache can hold the address 00000FOF?
Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) To which cache block will the memory address 0x01D872 map?
Suppose a computer using direct mapped cache has 224 bytes of byte- addressable main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. (Note: 64K = 26 * 210) a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?
[3] Suppose the RAM for a certain computer has 256M words, where each word is 16bits long. Note that you need to support your answer for each question in detail. (1) What is the capacity of this memory expressed in bytes? (2) If this RAM is byte addressable, how many bits must an address contain? (3) If this R AM is word addressable, how many bits must an address contain?
5. The ending address of a memory of size 1KB is 33FFH, then what is the starting address of the memory.
Memory system includes the elements: Main Memory=16 Mbytes, Cache=128Kbytes, Block= 8bytes. A) Design a direct-mapped cache memory system. (Draw the block diagram of the cache and mention on the diagram the values of: s, s+w, w, r, s-r) B) For the main memory addresses: 7AF9CD H show the following information, in hexadecimal format: a. Tag, Line, and Word values for a direct-mapped cache. b. Tag and Word values for an associative cache. c. Tag, Set, and Word values for a 4-way set associative cache.