Homework Help is Here – Start Your Trial Now!
Engineering
Computer Engineering
Q1:  Suppose the initial stack pointer of the interrupt stack is 0x81009A90, what is the value of SP after the interrupt handler has pushed the general purpose registers onto the interrupt stack? Q2: What is the value of the PC right before the general purpose registers have been pushed?   Q3: After the RFI instruction has completed, what is the value of the PC?   Q4: After the RFI instruction has completed, what is the value of the SP?

Q1:  Suppose the initial stack pointer of the interrupt stack is 0x81009A90, what is the value of SP after the interrupt handler has pushed the general purpose registers onto the interrupt stack? Q2: What is the value of the PC right before the general purpose registers have been pushed?   Q3: After the RFI instruction has completed, what is the value of the PC?   Q4: After the RFI instruction has completed, what is the value of the SP?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
See similar textbooks
icon
Related questions
Question

Q1: 

Suppose the initial stack pointer of the interrupt stack is 0x81009A90, what is the value of SP after the interrupt handler has pushed the general purpose registers onto the interrupt stack?

Q2:
What is the value of the PC right before the general purpose registers have been pushed?
 
Q3:
After the RFI instruction has completed, what is the value of the PC?
 
Q4:
After the RFI instruction has completed, what is the value of the SP?
Question 1: Pardon the interruption - Part II Suppose we have a 32-bit CPU. That is, "words" are 4 bytes long. This CPU requires all memory accesses to be word-aligned. The address space is split exactly in two, with the low addresses used for user processes and the high addresses used for the kernel. Each register contains exactly one word. The processor has 8 general purpose registers (R1 through R8). The stack "grows down" (i.e., when a word is pushed, the SP decreases by the size of a word in bytes). The SP points to the last word that was pushed. A PUSH instruction occupies exactly one word. When an interrupt occurs, the CPU disables interrupts and the user's PC, SP, and PSW are pushed onto the kernel stack. The SP register is loaded with the address of the top of the (empty) kernel stack saved in the process' PCB, and the PC is loaded from the interrupt vector according to the interrupt type. The RFI (Return-From- Interrupt) instruction restores the values PC, SP, and PSW by popping them from the kernel stack back to the corresponding registers. An RFI instruction also occupies exactly one word. The processor has the following interrupt vector: Type System Call Divide By Zero Disk Interrupt Illegal Memory Access Network Interrupt Clock Interrupt Handler Address 0x8001B040 0x8001B150 0x8001B280 0x8001B3B0 0x8001B490 0x8001B540 Each handler first pushes all general purpose registers before calling the C code that handles the rest of the interrupt. Upon return, the handler restores the general purpose registers by popping them off the interrupt stack, and executes the RFI instruction. Now suppose that a process is executing with PC = 0x0001 AC50 and SP = 0x7FFFEBAO when a Network Interrupt occurs. Answer the following questions. All answers must be in hexadecimal.
Transcribed Image Text:Question 1: Pardon the interruption - Part II Suppose we have a 32-bit CPU. That is, "words" are 4 bytes long. This CPU requires all memory accesses to be word-aligned. The address space is split exactly in two, with the low addresses used for user processes and the high addresses used for the kernel. Each register contains exactly one word. The processor has 8 general purpose registers (R1 through R8). The stack "grows down" (i.e., when a word is pushed, the SP decreases by the size of a word in bytes). The SP points to the last word that was pushed. A PUSH instruction occupies exactly one word. When an interrupt occurs, the CPU disables interrupts and the user's PC, SP, and PSW are pushed onto the kernel stack. The SP register is loaded with the address of the top of the (empty) kernel stack saved in the process' PCB, and the PC is loaded from the interrupt vector according to the interrupt type. The RFI (Return-From- Interrupt) instruction restores the values PC, SP, and PSW by popping them from the kernel stack back to the corresponding registers. An RFI instruction also occupies exactly one word. The processor has the following interrupt vector: Type System Call Divide By Zero Disk Interrupt Illegal Memory Access Network Interrupt Clock Interrupt Handler Address 0x8001B040 0x8001B150 0x8001B280 0x8001B3B0 0x8001B490 0x8001B540 Each handler first pushes all general purpose registers before calling the C code that handles the rest of the interrupt. Upon return, the handler restores the general purpose registers by popping them off the interrupt stack, and executes the RFI instruction. Now suppose that a process is executing with PC = 0x0001 AC50 and SP = 0x7FFFEBAO when a Network Interrupt occurs. Answer the following questions. All answers must be in hexadecimal.
Expert Solution
trending now

Trending now

This is a popular solution!

steps

Step by step

Solved in 6 steps

SEE SOLUTIONCheck out a sample Q&A here
Blurred answer
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY
SEE MORE TEXTBOOKS