A byte-addressable computer uses 32-bit address to access main memory. Suppose the data cache contains 128 blocks and works in4-way set-associative. Each block size is 64B with one "valid" bit. a. How many bits in Tag, Index and Offset? b. Calculate the total cache size (in bits).

Determine which bits in a 32-bit address are used for selecting the byte (B), selecting the word (W), indexing the cache (I), and the cache tag (T), for each of the following caches: B. 256-line, fully-associative, write back, 16 byte line

Consider a 64K L2 memory and a 4K L1 2-way associative cache with block sizes of 512. a. How many blocks are in each set in L1? b. How many offset bits are in the L2 address? c. How many index bits are in the L2 address? d. How many tag bits are in the L2 address?

If we had a computer that can only address data in bytes, but it has fully associative mapping, 16-bit main memory addresses, and 32-bit cache memory blocks. If each block is 16 bytes in size, then...(a) Count the number of bytes in the offset field.The tag field's size in pixels must be calculated (b).

Suppose we have a byte-addressable computer with a cache that holds 8 blocks of 4 bytes each.  Assuming that each memory address has 8 bits, to which cache block would the hexadecimal address 0x2D map if the computer uses direct mapping? Blocks are numbered starting at 0

Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) To which cache block will the memory address 0x01D872 map?

Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000

You are given a main memory of 64Mbytes with each byte addressable and asked to design a cache memory using direct mapping. The main memory is organized as blocks of 8bytes. The cache memory must have a size of 512Kbytes.     How many lines do you need to use in the cache memory?

Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?