onsider the function F(A,B,C)= A(B+C) + B’C + A’ and implement it using Universal Gates. i. NAND gates only. ii. NOR gates only.
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Q: How to make NAND gate using NOR gate only.
A: Assume two inputs are A and B Draw the logic diagram
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- 3-) Simplify the following Logic Function with Karnaugh diagram in Maxterm form and give the final form; Draw with 2 Input NOR gates only F(A,B,C) = A. (B.C + B'.C) + B. (A'.C' + A.C') + (A.B'.C')Simplify the following expressions, and implement them with two-level NAND gate circuits: (a) AB'+ABD + ABD’+A’C’D'+A’BC' (b) BD + BCD'+AB’C’D' Draw a logic diagram using only two-input NAND gates to implement the following expression: (AB + A’B') (CD'+C°D)3-) Make the following Logic Function with Karno diagram in Max.term form the simplest and give the final form; Draw with 2 Input NOR gates only F(A,B,C) = A. (B.C + B'.C) + B. (A'.C' + A.C') + (A.B'.C')
- Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions.Task 1: 2-to-1 LINE MULTIPLEXER DESIGNA) Write the truth table of 2-to-1 line multiplexer.B) Draw the circuit diagram by using only NAND & NOT GATES.C) Simulate the circuit that you found in part B.Lab# Introduction to Logic Gates +5V FLED U1 AND2EE U2 INVEE GND R1. R2 1K 1K GŇD 3) Verification the circuits by using switches, LEDS, and function generator The above circuit has two inputs (A and B). Connect AND gate's output and Inverter's output to two separate LEDS to test whether these two gates work properly. (You can also connect inputs of the AND gate to different LEDS - they will indicate logic levels on inputs.) Verify circuit function by providing inputs from two separate switches.
- 3. Logic Design a. Create the truth table of a 3-input AND gate. Realize the 3-input AND operation using only 2-input NOR gates. b. Create the truth table of a 3-input OR gate. Realize the 3-input OR operation using only 2- input NAND gates. c. Using AND and OR logic gates, implement the logic function: F(x, y, z) = xy + yz + zx d. Using NAND logic gates, implement the logic function: F(x, y, z) = xy + yz + zxConsider a family of logic gates that operate under the static discipline with the following voltage thresholds: VI=1.5V, VOL=0.5V, VIH=3.5V, and VOH=4.4V. a. What is the lowest voltage that can be output by an inverter for a logical 1 output? Why? b. What is the highest voltage that must be interpreted by a receiver as logical 0? Why? c. What is the lowest voltage that must be interpreted by a receiver as logical 1? Why?a) For the given logic circuit diagram write the program by using the gate level modeling. b) For the given truth table write the program by using the data flow Modelling. c) Write the test bench of the given logic circuit with all possibilities Y1 Y2 Y3 Y4 Y5 Y6 Y7 A2 A1 A0
- Draw a logic diagram using only two-input NAND gates to implement the following expression: (AB + A'B') (CD'+C'D)Draw the AND and OR gate logic diagram of the expression. X=L[K(K+L)+M] Logic diagram using AND-OR gates Redraw the circuit using positive NOR gates. Logic diagram using positive NOR gates K(SW2) 0 0 0 0 1 1 1 1 INPUTS L (SW3) 00 1 1 0 0 1 1 M(SW4) 0 1 0 1 0 1 0 1Which one of the following is the NAND2 gate equivalent area of the circuit A.B.C + C + D? The gate equivalent areas of 2-input logic gates are given in the reference section at the end of the question booklet. A. 6.6 GE B. 5.3 GE C. 5.9 GE D. 7.9 GE