Answer (a) Media applications that play audio or video files are part of a class of workloads called "streaming" workloads i.e., they bring in largeamounts of data but do not reuse much of it. Consider a video streaming workload that accesses a 512 KiB working set sequentiallywith the following address stream:0, 1, 2, 3, 4, 5, 6, 7, 8, 9....(a) Assume a 64 KiB direct-mapped cache with a 32-byte block. What is the miss rate for the address stream above? How is this missrate sensitive to the size of the cache or the working set? How would you categorize the misses this workload is experiencing,based on the 3C model?(b) Re-compute the miss rate when the cache block size is 16 bytes, 64 bytes, and 128 bytes. What kind of locality is this workloadexploiting?(c) "Prefetching" is a technique that leverages predictable address patterns to speculatively bring in additional cache blocks when aparticular cache block is accessed. One example of prefetching is a stream buffer that prefetches sequentially adjacent cacheblocks into a separate buffer when a particular cache block is brought in. If the data are found in the prefetch buffer, it isconsidered as a hit, moved into the cache, and the next cache block is prefetched. Assume a two-entry stream buffer; and,assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block iscompleted. What is the miss rate for the address stream above?

In computer architecture, a direct-mapped cache is one in which a main memory address is mapped to a…

Media applications that play audio or video files are part of a class of workloads called "streaming" workloads i.e., they bring in large amounts of data but do not reuse much of it. Consider a video streaming workload that accesses a 512 KiB working set sequentially with the following address stream: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9... (a) Assume a 64 KiB direct-mapped cache with a 32-byte block. What is the miss rate for the address stream above? How is this mis rate sensitive to the size of the cache or the working set? How would you categorize the misses this workload is experiencing, based on the 3C model?

Media applications that play audio or video files are part of a class of workloads called "streaming" workloads i.e., they bring in large amounts of data but do not reuse much of it. Consider a video streaming workload that accesses a 512 KiB working set sequentially with the following address stream: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9... (a) Assume a 64 KiB direct-mapped cache with a 32-byte block. What is the miss rate for the address stream above? How is this mis rate sensitive to the size of the cache or the working set? How would you categorize the misses this workload is experiencing, based on the 3C model?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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CA_10 Let the virtual address be V bits and the virtual addtess space be byte-addressable, the page size be P KB (and P is a power of 2), and the the main memory size be MM MB(where [MM MB]) is divide into [P KB]). (d)How many of the virtual memory bits need to be translated? (e) How many bits will be produced if the virtual-to-pyysical address translation is "successful" (f) How many bits does a physical address have, and how are each of these bits obtained?
NO PLAGARISM Assume that a main memory with only 4 frames each of 16 bytes is initially empty. The CPU generates the following sequence of virtual addresses and uses the Optimal Page replacement policy. 0,4,8,20,24,36,44,12,68,72,80,84,28,32,88,92 Your task is to find out the followings: a. How many page faults does this sequence cause? b. What are the page numbers of the pages which are present in the main memory at the end of the sequence? Assume that it is a byte addressable system.
A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?
You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, Given virtual address 0x06 converts to physical address 0x36. Show the format for a physical address (specify the field names and sizes) that is used to determine the cache location for this address. Explain how to use this format to determine where physical address 0x36 would be located in cache. (Hint: Convert 0x36 to binary and divide it into the appropriate fields.)
CA_10 Let the virtual address be V bits and the virtual addtess space be byte-addressable, the page size be P KB (and P is a power of 2), and the the main memory size be MM MB(where [MM MB]) is divide into [P KB]). (a) How large is the user's memory spac (b) How large is the main memory page frames? (c) How large is the page table (in number of table entries)? (d)How many of the virtual memory bits need to be translated? (e) How many bits will be produced if the virtual-to-pyysical address translation is "successful" (f) How many bits does a physical address have, and how are each of these bits obtained?
You have a virtual memory system with a two-entry TLB, a 2-way set associative cache and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided up into blocks, where each block is represented by a letter. Two blocks equals one frame. A) Virtual address page 3, offset 7 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame and what the physical address in binary? Explain your answers. B) Virtual address page 0, offset 1310 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers. C) Virtual address page 2, offset 3 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s…
In a main memory-disk virtual storage system, the page size is 1KByte and the OPTIMAL algorithm is used for page replacements. A given program has been allocated three page frames in the main memory and it makes the following 16 memory references when it starts executing (the addresses are given in decimal):500, 2000, 2500, 800, 4000, 1000, 5500, 1500, 2800, 400, 5000, 700, 2100, 3500, 900, 2400 Fill in the contents of the three page frames after each memory reference in a table and calculate the hit ratio. Hint: denote by 'a' the page consisting of locations 0 through 1023 in memory. Similarly, b: 1024-2047, c: 2048-3071, d: 3072-4095, e: 4096-5119 and f: 5120-6143. Round to three decimal places.
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
You are given the following data about a virtual memory system:(a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1nsec).(b) A page table entry can be found in 100 clock cycles or 100 nsec.(c) The average page replacement time is 9 msec.If page references are handled by the TLB 99% of the time, and only 0.01%lead to a page fault, what is the effective address-translation time?
Q3 Consider a swapping system in which main memory contains the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of (a) 12K, (b) 10K and (c) 9K for Next-Fit? Assume the last allocated hole is 20K.
Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. 8 bits are used for offset, 8 bits are used for page # and the max number of pages a process can have is 256. e. Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert hexadecimal numbers to decimal ones.) 0x0389 0xDF78 0x0245 0x8012 f) Now, suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) g)What is the size of the two-level page table…
Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. Could you hand draw the page table, if possible a) Suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) b) What is the size of the two-level page table