Implement the following Boolean function with a 4 x 1 multiplexer and external gates. Connect inputs A and B to the selection lines. The input requirements for the four data lines will be a function of variables C and D. These values are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01, 10, and 11. These functions may have to be implemented with external gates. F(A, B, C, D) = E(1, 3, 4, 10,11, 12, 13, 14, 15)
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- USE DIGITAL LOGIC AND DESIGN Part 1: In Figure_4; we have 4-bit Comparator using 2-bit Comparators block. You have to satisfy given condition by applying all data on figure 4. At the end, given condition should produce HIGH output and other two should be LOW. A3 A2 A1 A0 = 1101 and B3 B2 B1 B0 = 1110 Figure_4 Part 2: The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in Figure_5. Determine the data-output waveforms from D0 through D3. Figure_5 Part 3: Decoder can be useful when we have to decode some specific numbers from their equivalent code. Figure 6 has a concept of 3 to 8 line decoder from which you have to generate output waveform from D0 to D7 with proper relationship to input. Figure_6 Part 4: The data-input and…The following waveforms are the input to the shift register you constructed in question #5. Based onthe waveforms for the CLK (clock) and D0 input (input on the leftmost Flipflop), generate thewaveforms for Q0, Q1, Q2, Q3, Q4. (Question #5 is "Using JK-Flipflops and Digital Logic Gates, build a 5-stage Shift Register")For a ((A+B)' + (A'B')) Boolean equation, with the input waveforms as shown in Figure 2, which output waveform is correct? INPUT A INPUT B OUTPUT a OUTPUT b OUTPUT C OUTPUT d- Figure 2 Output b Output a Output d Output c A full adder logic circuit has Three inputs and three outputs. Three inputs and two outputs. Two inputs and one output. Two inputs and two outputs.
- 3- A-) Implement the Boolean function (F) with a 4 X1 multiplexer and two-input-NOR gates. Connect inputs A and B to the selection lines. The input requirement for the four data lines will be a function of variables C and D. These values are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01 ,10 and 11. B-) Implement the Boolean function with a 8 X 1 multiplexer. Connect inputs A,B and C to selection lines. F(A, B, С, D) - 2 (1, 3, 5, 9, 10, 14, 15) А So В S1 4 x 1 MUX 1 Y F 2 3H.W :- 1) A four logic-signal A,B,C,D are being used to represent a 4-bit binary number with A as the LSB and D as the MSB. The binary inputs are fed to a logic circuit that produces a logic 1 (HIGH) output only when the binary number is greater than 01102-610. Design this circuit. 2) repeat problem 1 for the output will be 0 (LOW) when the binary input is less than 01112-710- Saleem LateefDesign a code converter that converts a decimal digit from BCD to excess-3 code, the input variables are organized as (A BC D) respectively with A is the MSB, the output variables are organized as (W X Y Z) respectively with W is the MSB, put the invalid decimal numbers as don't care. X= BCD'+B'D+B'C X= BC'D'+B'D+BC X= BC'D'+B'D+B'C X= BC'D'+BD+B'C
- Answer the following questions: 1. Design a 8 bit "shift left-shift right" register. 2. Design a 8 bit up counter. 3. Difference between sequential circuit vs combinational circuit. 4. Design a 8:1 multiplexer using 4:1 multiplexer and 2:1 multiplexer. 5. When designing register file, we used multiplexer to read from a specific register of that register file. However, to write in the register file, we didn't use demultiplexer. Why ? 6. In our designed register file, we can write one data at a time. But if we want to write two data at a time,what should we do ? 7.Logisim simulation: A. Design a 8 bit register file with 10 registers. B. Design an ALU with AND, OR, XOR, NOT, ADD and SUBTRUCT operations that can use the above register file. C. Create a single cycle data-path between register file and ALU. Save 1 digit of your NSU ID in each register of your register file before running instructions given below.E.g. for id: 1831565042, save 1 in first register, 8 in second, 3 in third and…Design a combinational circuit with the four inputs A,B.C, and D, and three outputs X, Y, and Z. When the binary input is odd number, the binary output is one lesser than the input. When the binary input is even number the binary output is one greate than the input. Implement the function using multiplexers with minimal input and select line.Draw a dataflow circuit using block components that lets you add or subtract two input numbers in all possible ways. Your circuit will have two inputs X, Y and one output Out. You’ll have an adder and you’ll need to use multiplexers on each input to the adder. Clearly specify the number and type of control bits needed.
- The numbers from 0-9 and a no characters is the Basic 1 digit seven segment display * .can show False True In a (CA) method of 7 segments, the anodes of all the LED segments are * "connected to the logic "O False True Some times may run out of pins on your Arduino board and need to not extend it * .with shift registers True FalseConsider a 2-bit parallel adder with ripple carry. It uses two full adders. It adds A1A0 to B1B0. Draw the adder and show all connections. Assuming that this adder will only add vectors (A1A0B1B0) that have odd parity AND neither number is 00, what is the average delay of the adder given that the outputs are initially high till the correct output is produced? Assume that the delay of a full adder is 6nsec.A state machine can detect when it has received the serial input sequence 011. The input of the machine is 0 or 1.a. Draw state diagramb. Make table of state transitionc. Make the Boolean equation and simplifyd. Draw the circuit of FSM