2. Implement the Boolean expression: F (A, B, C, D) = (1,3, 4, 11, 12, 13, 14,15) Using a 8 to 1 Mux 3. What are the applications of multiplexer and de-multiplexer?
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- Design a combinational circuit with the four inputs A,B.C, and D, and three outputs X, Y, and Z. When the binary input is odd number, the binary output is one lesser than the input. When the binary input is even number the binary output is one greate than the input. Implement the function using multiplexers with minimal input and select line.Write a VHDL code for the following simple logic circuit. D- X1 X2 f X3To implement a Full Subtracter, Using TWO 8:1 Multiplexers (ONE for Sum output and ONE for Cout output). Assign (or Connect) X, Y,and Bin variables to the Select Inputs of Multiplexers and connect 1 or 0 to each Data Input.
- USE DIGITAL LOGIC AND DESIGN Part 1: In Figure_4; we have 4-bit Comparator using 2-bit Comparators block. You have to satisfy given condition by applying all data on figure 4. At the end, given condition should produce HIGH output and other two should be LOW. A3 A2 A1 A0 = 1101 and B3 B2 B1 B0 = 1110 Figure_4 Part 2: The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in Figure_5. Determine the data-output waveforms from D0 through D3. Figure_5 Part 3: Decoder can be useful when we have to decode some specific numbers from their equivalent code. Figure 6 has a concept of 3 to 8 line decoder from which you have to generate output waveform from D0 to D7 with proper relationship to input. Figure_6 Part 4: The data-input and…H.W :- 1) A four logic-signal A,B,C,D are being used to represent a 4-bit binary number with A as the LSB and D as the MSB. The binary inputs are fed to a logic circuit that produces a logic 1 (HIGH) output only when the binary number is greater than 01102-610. Design this circuit. 2) repeat problem 1 for the output will be 0 (LOW) when the binary input is less than 01112-710- Saleem LateefDesign the interfacing circuit shown below and write a program to display single digit (between 0 and 9) prime numbers followed by even numbers, the next odd numbers and repeats in 7-segment displays and its equivalent 8-bit binary value in LEDS. a) When displaying Prime numbers, the first 7-segment display must show "P" and the second 7-segment display must show prime numbers one by one b) When displaying Even numbers, the first 7-segment display must show "E" and the second 7-segment display must show even numbers one by one c) When displaying Odd numbers, the first 7-segment display must show "O" and the second 7-segment display must show even numbers one by one
- Which function performs the following operation? Give the assembly instruction and show your work. Before A= 11011011, CF=1 After A= 10111101, CF=11. Gray code to Binary converter: Gray code is one of the codes used in digital systems. It has the advantage over binary numbers that only one bit in the code word changes when going from one number to the next. (See Table 1). Design a combinational circuit with 4 inputs and 4 outputs that converts a four- bit gray code number into an equivalent four-bit Binary number. Use Karnaugh map technique for simplification. Use LogicWorks for pre-lab demonstrations. Select the library "7400dev.clf* in the Parts Palette and then select the XOR chip 74-86. This would give you a set of 4 XOR's as shown in Fig. 1, just like the hardware chip 74-86. You could use as many as needed from these XOR gates in your design. Get back to ALL LIBRARIES and select switches for the inputs and Binary Probes as indicators of the outputs. Verify your design in the pre-Lab. During the Lab construct the circuit and verify its operations.answere fast please question from DIGITAL LOGIC DESIGN TOPIC : Designing Combinational Logic You are designing a water level circuit using 74ALS151 (8 to 1 Multiplexer IC)* When input is 0000 that means tank is empty.* When input is 1111 that means tank is full.* When input is below 5, that means water level is low.* So, make a circuit using 74ALS151 Multiplexer IC that shows a "low water" indicator light(by setting an output L to 1) when the water level drops below level 5.
- The following waveforms are the input to the shift register you constructed in question #5. Based onthe waveforms for the CLK (clock) and D0 input (input on the leftmost Flipflop), generate thewaveforms for Q0, Q1, Q2, Q3, Q4. (Question #5 is "Using JK-Flipflops and Digital Logic Gates, build a 5-stage Shift Register")Digital logic design Solve it with drawing and simulation lab I need them both to have the full solution. And thanks Design counter that counts from 00 to 59, using the IC 74LS90 ripple counter and use two 7 segment display to display the result count. You can also use 7447 binary to 7-segment Display Decoder.Q5 (a) Discuss, the major dıfferences between ticld programmable gatc arrays (FPGAS) and programmable logie devices (PLDS. where an FPGA may be approprate in a streamıng TV system. Simple multiplexers can be used to mimic a number of two-input logic functions by appropriate mapping of nputs X X, and SEL Show how the multiplexer shown in figure Q5a can be used to perform the function F= AOB (b) SEL Figure Q5a Figure Q5b (over) shows the schematic of a Xilinx 3000 sennes logic cell M Label the configuration bits of the various multiplexers n the celL with zeroed configuration bits selecting the topmost input to each multuplexer. Each multiplexer has -2 ns, the combinatorial loge block is guaranteed to have WS7 ns, and the D-type flip-flops have t4 ns and r 1 ns (c) We wish to construct a two-bit counter from this logie cell. where Q, and Q are the high and low order outputs of the counter, CLK is the clock signal, AR is an asynchronous reset signal, EN enables the counter, and LD allows…