Why is it preferable to use segmented memory address translation instead of just translating the addresses directly?

Convert the following Compact Memory Notation diagram into an Array Memory Notation diagram. Assume the addresses are 4-bit binary values and the data are 8-bit binary values. Hint: The solution to this question is simply the reformatted diagram in Array Notation.

Suppose the RAM for a certain computer has 4M words, where each word is 16 bits long. What is the capacity of this memory expressed in bytes? If this RAM is byte addressable, how many bits must an address contain? If this RAM is word addressable, how many bits must an address contain?

The memory size might be specified as follows: Memory Size = Number of Words x The number of bits in a word What is the number of address and data lines necessary to build a 256 X 32 memory circuit utilising a decoder and a multiplexer?