Explain about TLB, page table, and cache for small memory system ?

For a computer with 56-bit physical addresses and a 8-way set associative cache of 64 KB where each cache line has the capacity of holding 32 words. Assume the word size is 3 and the architecture is byte-addressable. Answer the questions below: a.How many bits are needed for tag, index, word offset, and byte offs. Show your derivations and assumptions. b.What are the start and end physical addresses, in hex as discussed in class, for cache line 300? Cache line count starts from 0. c.What is the total size, in KB, of this cache? d.What is the tag value, in hex, of address 0xABCDEF98765432?

A time diagram for Direct Memory Access (DMA) that takes into account clock synchronization?

8. In two-stage addressing of DRAM, with an addition of a single address line, how is amount of memory addressed changed? 9. Describe / model the Memory Organization of DRAM using two-stage addressing (a simple model is all that is needed for the description).