Every rotation of a motor causes a switch to be pushed. The switch, like most mechanical switches, 'clatters' or bounces when the contacts come together, causing an interval when a single press causes multiple closures. This bouncing can continue for just under 3 milliseconds. The switch is linked into the memory map of a 68000 processor at bit 0 of location $FFFFF000. It is connected so that the bit will read a '1' when the switch is open, and a '0' when closed and not bouncing. The bouncing will cause alternating zeros and ones. For ease of any analysis you do, assume that every instruction takes 1 usec., regardless of addressing mode. If the switch were connected to a falling-edge-sensitive interrupt request line what problem could result during the bouncing? And what is one way the problem might be solved?

ssembly language

CLK signal is the clock output 1 point signal provides the basic timing for processor operation and bus control activity * True O False

Task 1 Write a program that adds the three numbers stored in data registers at 0x20, 0x30, and Ox40 and places the sum in data register at 0x50. Step 1 Load the number of 0x20 into the WREG register Step 2 Add the number of 0x30 and the number in the WREG register and leave the sum in the WREG register. Step 3 Add the number of Ox40 and the number in the WREG register and leave the sum in the WREG register. Step 4 Store the contents of the WREG register in the memory location at 0x50. Modify the program in Task1, so the program will run in infinite loop by using these following functions: ii. BRA function