Discussion: 1. Implement the Boolean expression: F( x, y, z) = (1, 2, 6, 7) Using a 8 to 1 Mux 2 Implement the Boolean evpression:
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A: Apply Boolean Laws: According to annulment law, A.0 = 0 And, according to complement law, A.A' = 0
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- Design a combinational circuit with the four inputs A,B.C, and D, and three outputs X, Y, and Z. When the binary input is odd number, the binary output is one lesser than the input. When the binary input is even number the binary output is one greate than the input. Implement the function using multiplexers with minimal input and select line.A digital circuit's input X (X3,..., Xo) represents a four-bit unsigned number from 0 to 6. The output of the circuit: Y = -X For don't cares, the outputs are set to 0's. Use a multiplexer to implement only the most-significant bit (MSB) of the circuit output. From the list below, select the correct set of multiplexer inputs. Draw (on paper) fully-labeled circuit diagram. (Include complete solution ir the test/exam PDF file). (a) D, 1, 1, D, 0,0, 0,0 (b) D, D, 0,0, 0, 1,0, 1 MacBook AirYour task is to implement a Full Adder(a) Using TWO 8:1 Multiplexers (ONE for Sum output and ONE for Cout output). Assign (or Connect) X, Y,and Cin variables to the Select Inputs of Multiplexers and connect 1 or 0 to each Data Input.
- 3) Show how two 4:1 and one 2:1 mux could be connected to form an 8:1 mux. 4) Given the multiplexer below, what is Boolean function J(A,B,C)? Write your answer in Em notation. C 4X1 >J MUX "1L A BDesign the interfacing circuit shown below and write a program to display single digit (between 0 and 9) prime numbers followed by even numbers, the next odd numbers and repeats in 7-segment displays and its equivalent 8-bit binary value in LEDS. a) When displaying Prime numbers, the first 7-segment display must show "P" and the second 7-segment display must show prime numbers one by one b) When displaying Even numbers, the first 7-segment display must show "E" and the second 7-segment display must show even numbers one by one c) When displaying Odd numbers, the first 7-segment display must show "O" and the second 7-segment display must show even numbers one by oneConsider a uniform quantizer that uses 3 bits and whose input ranges from -1 V to +1 V. a. How many signal levels are present after the quantizer? b. How large is the quantization step for this quantizer? Provide your answer with 4 significant figures. c. How large is the quantization noise in this quantizer in mW? Provide your answer with 4 significant figures.
- 2. Design an electronic digital circuit that implements the following logic expressions. Hint: Consider a multiplexer approach as your first optimization alternative. F = A-B.C+ B.T D+C D+ A C.D+A.B F = A.B.C+ B.C.D+C D+A C-D+C D A-B.C+A.B -D+T D+A.C-D+C.D A.B.C+B C.D+C.D+ A.C-D+ A.B F = (7.2) Construct K-Maps for all expressions Construct the optimized circuit that best meets specifications 7.2.- The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates. - Set up the circuits you designed with NAND and NOR gates and observe the outputs. Show the output values by drawing a table, applying all possibilities to the input values.- The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates.
- A 4-bit magnitude comparator is explained in the attached file. With similarlogic, design a 3 bit magnitude comparator. You must show the equations and draw the logic circuit. [Hints: A and B are two numbers each with 3 bits. How can you implement a circuit to compare these two numbers if, A=B, A>B or A<B]Write a VHDL code for the following simple logic circuit. D- X1 X2 f X33-) Analyze the circuits below and write the Boolean equation for each Part. Simplify the equation using Boolean algebra and determine if they function as an XOR, XNOR or neither. A): Dor B): XD XD . D