Design and implement using T-FF a synchronous loop counter that counts: 5--->3---> 0---->1---->6 and back to 5 in a loop. Use a circuit simulation software to implement the counter circuit.

Design a 16 bit adder/subtractor with 2 data inputs (B15 to B0 and A15 to A0), a SEL input (1 if add and 0 if subtract), and a result output (R15 to R0).You can design the circuit in MultiSim, VHDL, or LabVIEW. PLEAE USE MULTISIM

Draw the logic diagram using only two input NAND gates to implement we following expression F = (AB + AB)(CD + CD).

Assume we are writing a testbench for a sequential circuit that has three control inputs (cA, cB, cC) and a periodic clock (clk). If we define CLK_PERIOD as a localparameter with a value of 50 (nsec), write the testbench segment that would ensure all possible combinations of the control inputs were tested on a clock rising edge. This is can be done more elegantly if you define each time step in terms of the constant CLK_PERIOD. Your answer should include the statements that define clk, cA, cB, and cC over time. Hint: think of how you would show all combinations of three variables on a truth table and replicate that over time, where each combination is held over a timespan with a clock triggering edge.

i need help with the step 4 part mainly. ive already done the verilog and gotten that schematic.

Use SOP and POS and draw the schematic diagram

Question 4: Design and implement a minimal 5 modulo up counter. It counts from 0 to 4 and repeats. Design the circuit such that, if the counter enters into the unwanted states: 5, 6 and 7, it should jump into state 0 on the next clock pulse.

Design and implement using T-FF a synchronous loop counter that counts: 5>3>0>1>6 and back to 5 in a loop. Use the Tina software to implement the circuit of the counter.

boolean expression: P = not((not(a.b) + c) + a.c)  (c) Show that P (the Boolean expression above) is equivalent to the Boolean expression Q = a · b · not(c) and draw the corresponding circuit.

Create a circuit for detecting 1110 in a sequential machine. In the process draw the state diagram for overlapping,transition table, k-map and finally the circuit diagram.