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Based on Slide #27 1. From the state-assigned table, derive (backwards) the stage diagram (Moore). 2. Develop the Verilog code using the template. 3. Obtain the schematic 4. Based on the state-assigned table, derive the circuit using Boolean logic. Using Kmap and Boolean logic to get the next state logic and the output logic. Derive the circuit with D flip-flops based on the logics you derived. 5. Compare the two schematics, and document it in a word file. Exercise 2 An FSM is defined by the state table below. Is this Moore or Mealy? Derive the circuit using D flip-flops. Then implement it with Verilog code using the template module. Compare the schematic with the derived circuit. Present Next state state w = 0 w = 1 Output y2y1 Z Y2Y1 Y2Y1 00 10 11 0 01 01 00 0 10 11 00 1 10 01 1 4/8/2024 ECE3300 Meng-Lai Yin 24 27

Based on Slide #27 1. From the state-assigned table, derive (backwards) the stage diagram (Moore). 2. Develop the Verilog code using the template. 3. Obtain the schematic 4. Based on the state-assigned table, derive the circuit using Boolean logic. Using Kmap and Boolean logic to get the next state logic and the output logic. Derive the circuit with D flip-flops based on the logics you derived. 5. Compare the two schematics, and document it in a word file. Exercise 2 An FSM is defined by the state table below. Is this Moore or Mealy? Derive the circuit using D flip-flops. Then implement it with Verilog code using the template module. Compare the schematic with the derived circuit. Present Next state state w = 0 w = 1 Output y2y1 Z Y2Y1 Y2Y1 00 10 11 0 01 01 00 0 10 11 00 1 10 01 1 4/8/2024 ECE3300 Meng-Lai Yin 24 27

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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i need help with the step 4 part mainly. ive already done the verilog and gotten that schematic.

Based on Slide #27 1. From the state-assigned table, derive (backwards) the stage diagram (Moore). 2. Develop the Verilog code using the template. 3. Obtain the schematic 4. Based on the state-assigned table, derive the circuit using Boolean logic. Using Kmap and Boolean logic to get the next state logic and the output logic. Derive the circuit with D flip-flops based on the logics you derived. 5. Compare the two schematics, and document it in a word file.
Transcribed Image Text:Based on Slide #27 1. From the state-assigned table, derive (backwards) the stage diagram (Moore). 2. Develop the Verilog code using the template. 3. Obtain the schematic 4. Based on the state-assigned table, derive the circuit using Boolean logic. Using Kmap and Boolean logic to get the next state logic and the output logic. Derive the circuit with D flip-flops based on the logics you derived. 5. Compare the two schematics, and document it in a word file.
Exercise 2 An FSM is defined by the state table below. Is this Moore or Mealy? Derive the circuit using D flip-flops. Then implement it with Verilog code using the template module. Compare the schematic with the derived circuit. Present Next state state w = 0 w = 1 Output y2y1 Z Y2Y1 Y2Y1 00 10 11 0 01 01 00 0 10 11 00 1 10 01 1 4/8/2024 ECE3300 Meng-Lai Yin 24 27
Transcribed Image Text:Exercise 2 An FSM is defined by the state table below. Is this Moore or Mealy? Derive the circuit using D flip-flops. Then implement it with Verilog code using the template module. Compare the schematic with the derived circuit. Present Next state state w = 0 w = 1 Output y2y1 Z Y2Y1 Y2Y1 00 10 11 0 01 01 00 0 10 11 00 1 10 01 1 4/8/2024 ECE3300 Meng-Lai Yin 24 27
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