Consider the following situation: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Based on the fact that each block has 8 bytes, figure out how big the offset field should be, and then show your work.

For a computer with 56-bit physical addresses and a 8-way set associative cache of 64 KB where each cache line has the capacity of holding 32 words. Assume the word size is 3 and the architecture is byte-addressable. Answer the questions below: a.How many bits are needed for tag, index, word offset, and byte offs. Show your derivations and assumptions. b.What are the start and end physical addresses, in hex as discussed in class, for cache line 300? Cache line count starts from 0. c.What is the total size, in KB, of this cache? d.What is the tag value, in hex, of address 0xABCDEF98765432?

Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size: a) Determine how many bytes the offset field is. Measure the tag field's width and height in pixels (b).

Consider a demand-paging system with a paging disk that has an average access/transfer time of 50 ms. Addresses are translated through a page table in main memory, with an access time of 500 ns per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added a TLB that reduces access time to one memory reference if the page-table entry is in the TLB. Assume that 80% of the accesses are in the TLB and that, of those remaining, 15% (or 3% of the total) cause page faults. We assume that the TLB access time is 20 ns. What is the effective access time?