Calculate the CPU execution time (expressed in milliseconds) of a program with 10 million instructions on a 2.5 GHz CPU with the following basic instruction-type breakdowns and CPIs: Arithmetic: 60%, CPI = 2 Load & Store (assuming perfect caches): 25%, CPI = 5 Branching: 15%, CPI = 3 In addition, you are told that the overall cache miss rate for instructions is 1%, the overall cache miss rate for data is 3%, and the cache miss penalty is 100 cycles. You can ignore the hit time (consider it zero).
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- A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses?A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the…A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the fictitious run time if there were no cache misses at all?
- Given the following memory addresses and opcodes to be executed, if the current value of the Instruction Register (IR) is EBOA, what is the value of the Instruction Pointer Register (RIP) after the instruction in IR is executed? 00000000 EBOA 00000002 B805000000 00000007 BF01000000 0000000C BAODO00000 00000002 00000007 0000000A 0000000CThe jump instruction (j) allows the execution to start from a new address. Opcode (6 bits) Address (26 bits) All of the following values are in decimal. If the PC current value is 8000 and we would like to use a jump instruction to start executing at a new address (20000), then the value of the address field (in decimal) should be: a. 12000 Ob. 20000 O c. 5000 d. 6000 O e. 4000Suppose you have a processor with a base CPI of 1.0, and two caches (L1 and L2). You have the following specifications Clock rate= 5 GHz. Access time to L2 Cache = 6 ns Access time to Main memory = 100 ns Miss rate per instruction at the L1 cache is 2.5%. Miss rate per instruction at the L2 cache is 0.7%. A program contains 3000 instructions, 600 of them are memory access instructions. Taking into consideration the stalls on Data cache only, find the total average CPI. a.2.63 b.None of them c.1.16 d.1.45 e.2.13
- A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode(four bus clock cycles),fetch operand address (three cycles), fetch operand (three cycles) add 1 to operand (three cycles), and store operand (three cycles). a. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? b. repeat assuming that the increment operation takes 13 cycles instead of 3 cyclesRequired reference strings needed for the Execution is given below 1000 AA 1002 AC 1004 DA 1006 CC 1008 1010 1012 65 DE AA 1014 1016 ЕЕ FF Can you map the required program with the virtual memory mapping. Main memory can hold 5K lines ( 1K per line) and cache memory size is 3k.A cache has a hit time Tc = 2 cycles and a miss rate Pmiss = 0.04. The main memory access time is Tmm = 36 cycles. The data-cache and instruction-cache have identical performance. A program has the following instruction distribution: probability of 0.3 for R-type instructions, 0.2 for load, 0.1 for store, and others for control instructions. Assume control instructions do not cause any loss. The processor is running at 1 GHz. Evaluate the average access time in nano-seconds of the memory system.
- Question 6 Suppose you have a RISC machine with a 1.6 GHz clock (i.e., the clock ticks 1.6 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: set reg, immed 2 clock cycle 2 clock cycles 2 clock cycle 4 clock cycles 3 clock cycles loop label add reg, immed add reg, reg load reg, mem Assume that the following code franent is used to sum the element of a numeric array. If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in 5 ms? Round your answer to the nearest integer. Recall that 1 ms = 0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired. ri, e r2, MAX_SIZE ;initialize loop counter r3, @list initialize sum set set set initialize array pointer more: load…A computer has a 256K word addressable memory Module with 16 bits per word. The instruction set consists of 166 different instructions. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. Based on the above, answer the following questions: a. How many bits are there in the main memory? (Represent it in power of 2) b. How many bits are needed for the opcode? c. How many bits are left for the address part of the instruction? d. How many additional instructions can be added to the existing 166 without affecting the assigned size of the opcode part? Justify.Consider a processor running a program. 30% of the instructions of which require a memory read or write operation if the cache bit ratio is 0.95 for instructions and 0.9 for data. When a cache bit occurs for instruction or for data, only one clock is needed while the cache miss penalty is 17 clocks to read/write on the main memory. Work out the time saved by using the cache, given the total number of instructions executed is 1 million.