Briefly describe the following: a. Configurable logic blocks b. "Synthesis" process in FPGA c. Timing diagrams d. Differentiate between reg and wire in Verilog e. How to add delay in Verilog testbench. Give a simple example

1. 3x8 Decoder Circuit (FULL Logic Circuit)

Explanation about (Deal with operational amplifier controllers and programmable logic controllers)

If R0 = 0x20008000, after run STMDB r0!, {r3, r9, r7, r1, r2} command what is the r7 register memory start address?A. R0= 0x20007ff4B. R0 = 0x20007ffefC. R0 = 0x20007fffD. R0=0x20007fecE. R0 = 0x20007ff0

Draw the complete logic circuit using pic16f84a microcontroller and write the necessary code that generates the A, B, and C waveforms simultaneously and periodically. The circuit must include power supply, clock oscillator, and reset circuit with following specifications: instruction cycle is 1 microsecond with a high accuracy; Proper working supply voltage >= 4.5 volts. 6 ms 5 volts B

Please do part b using the Assumption

A 16-bit successive approximation ADC is to be designed to operate at 50,000 conversions/second. What is the clock frequency? How rapidly mustthe unknown and reference voltage switches change state if the switch timing delay is to be equivalent to less than 0.1 LSB time?

(b) Figure Q.2.2 shows a simplified logic circuit of function X(A,B,C). X is a two- input primitive logic gate. Given that: 0(0,0,0) =0(0,2,4,5,6) Determine the type of logic gate X. Show your working steps. A B ar C Figure Q.2.2: Simplified logic circuit for function Y X

Suppose we have two registers, Rl and R2, and between them we have a combinational logic circuit. The tpcg = 0.5 ns, tccq = 0.25 ns, tpd = 4 ns, tcd = 2.5 ns, tsetup = 0.5 ns and thold = 0.2 ns. What is the maximum value of fc? Select one: a. 0.2 ps O b. 200 MHz O c. 2 GHz O d. 200 KHz

1- Explain the meaning and operation of CMC instruction ? 2. The Instruction Pointer is bits in length. a) 8 bits b) 4 bits c) 16 bits d) 32 bits