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A simple microprocessor is to have a watchdog timer installed. This timer will interrupt the processor unless it is constantly reset by the processor which it would normally do. This interrupt would happen if the processor went 'off the rails' because of a software problem, a power spike or something like that. A circuit diagram is started below. The timer in the diagram gives a single positivegoing pulse which can be extended by 'retriggering' using the reset line. Some information about the timer and use are given on the diagrams. The interrupt line is shared by other devices and is active when low. In the scheme to be used, the processor will reset the timer (and thus avoid the interrupt) by accessing a specific address, $FFE0, faster than the pulse time of the timer, thus restarting the pulse without an interrupt being generated. Timer: Relationship between reset input and the output: T= pulse time out reset Retrigger holds output pulse high Use of watchdog: out Causes cpu interrupt reset cpu goes off rails and no longer resets timer at intervals Less than

A simple microprocessor is to have a watchdog timer installed. This timer will interrupt the processor unless it is constantly reset by the processor which it would normally do. This interrupt would happen if the processor went 'off the rails' because of a software problem, a power spike or something like that. A circuit diagram is started below. The timer in the diagram gives a single positivegoing pulse which can be extended by 'retriggering' using the reset line. Some information about the timer and use are given on the diagrams. The interrupt line is shared by other devices and is active when low. In the scheme to be used, the processor will reset the timer (and thus avoid the interrupt) by accessing a specific address, $FFE0, faster than the pulse time of the timer, thus restarting the pulse without an interrupt being generated. Timer: Relationship between reset input and the output: T= pulse time out reset Retrigger holds output pulse high Use of watchdog: out Causes cpu interrupt reset cpu goes off rails and no longer resets timer at intervals Less than

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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A simple microprocessor is to have a watchdog timer installed. This timer will interrupt the processor unless it is constantly reset by the processor which it would normally do. This interrupt would happen if the processor went 'off the rails' because of a software problem, a power spike or something like that. A circuit diagram is started below. The timer in the diagram gives a single positivegoing pulse which can be extended by 'retriggering' using the reset line. Some information about the timer and use are given on the diagrams. The interrupt line is shared by other devices and is active when low. In the scheme to be used, the processor will reset the timer (and thus avoid the interrupt) by accessing a specific address, $FFE0, faster than the pulse time of the timer, thus restarting the pulse without an interrupt being generated. Timer: Relationship between reset input and the output: T= pulse time out reset -Retrigger holds output pulse high Use of watchdog: out Causes cpu interrupt reset cpu goes off rails and no longer Less than resets timer at intervals
Transcribed Image Text:A simple microprocessor is to have a watchdog timer installed. This timer will interrupt the processor unless it is constantly reset by the processor which it would normally do. This interrupt would happen if the processor went 'off the rails' because of a software problem, a power spike or something like that. A circuit diagram is started below. The timer in the diagram gives a single positivegoing pulse which can be extended by 'retriggering' using the reset line. Some information about the timer and use are given on the diagrams. The interrupt line is shared by other devices and is active when low. In the scheme to be used, the processor will reset the timer (and thus avoid the interrupt) by accessing a specific address, $FFE0, faster than the pulse time of the timer, thus restarting the pulse without an interrupt being generated. Timer: Relationship between reset input and the output: T= pulse time out reset -Retrigger holds output pulse high Use of watchdog: out Causes cpu interrupt reset cpu goes off rails and no longer Less than resets timer at intervals
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