A microprocessor has an increment memory direct instruction, which adds 1 to the value in memory location. The instruction has five stages:  fetch opcode (four bus clock cycles); fetch operand address (three bus clock cyles); fetch operand (three bus clock cyles); add 1 to operand (three bus clock cyles); and, store operand (three bus clock cyles). By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? Repeat assuming that the increment operation takes 13 cycles instead of 3 cycles.

20. Suppose we have just found yet another representation for floating point numbers. Using this representation, a li2-bit floating point number has 1 bit for the sign of the number, 4 bits for the exponent and 7 bits for the mantissa, which is normalized as in the Simple Model so that the first digit to the right of the radix points must be a 1. Numbers in the exponent are in signed 2's complement representation. No bias is used and there are no implied bits. Show the representation for the smallest positive number this machine can represent using the following format (simply fill in the squares provided). What decimal number does this equate to? : SIGN EXPONENT MANTISSA

18.) Choose the 8088 signals that are used to generate ROMRD. a.) IORD b.) IO/M c.) ALE d.) WR e.) RD

2. What are the basic five stages of the RISC pipeline, and explain the functions of each stage