A- How many clock states are in a read bus cycle that has no wait states? What would be the duration of this bus cycle if the 8086 were operating at 10 MHZ? B- In a maximum-mode 8086 microcomputer, what code is output on S453 when an instruction-fetch bus cycle is in progress?

JP Consider the four- input NOR logic gate in figure below, The transistor parameters are VTNL =-IV, and VTND = 0.5V. The maximum value of Vo in its low state is to be 0.2 V. Determine :- kn = 80 a) KD/KL b) The maximum power dissipation in the NOR logic gate is to be o.1 mW. find (W/L) c) to when VA = VB = Vc = VD = 3 V. 3v MA VB VTNL=-1V KL MB Mc whether with whee MD VTND 30.5V KD

Define a 2-bit demultiplexer to be a circuit whose single input line is steered to one of the four output linesdepending on the state of the two control lines (A, B). Draw its logic diagram (to the gate level) and specify the exactstate of A and B for each output line when that output line is selected.

Each frame (cycle) of E-1 PCM system is containing? a. 264 bits; b. 128 bits; c. 254 bits; d. 256 bits; e. different from the above number of bits.