A high-speed CMOS microprocessor has a 64-bitaddress bus and performs a memory access every2 ns. Assume that all address bits change duringevery memory access and that each bus line representsa load of 25 pF. (a) How much power is beingdissipated by the circuits that are driving these signalsif the power supply is 2.5 V? (b) Repeat for3.3 V.

Each frame (cycle) of E-1 PCM system is containing? a. 264 bits; b. 128 bits; c. 254 bits; d. 256 bits; e. different from the above number of bits.

2. (CMOS Network) Construct a truth table for the following circuit. 3v 0 A B C -Z ABCZ 3. (Logic Expression) For the circuit in question 2 obtain a logic expression (in terms of AND, OR, etc.) for the output Z.

a) A standard TTL inverter gate is shown in the figure. The supply voltage is 5V. Calculate the output voltage for both logic low and logic high input cases assuming input voltages respectively as 0.11V and 4.2V. Br= 130; BR = 0.24. You can make approximations when needed. Br = IcIs active region; BR = IE/ls inverse active region b) Assume you connect a resistor of 1.8K to the output of the circuit when the output is at logic high. What will be the change in the output voltage? 1302 R3 1.6k2 R, 4k2 Input o T, Output T, V, V. IkQ R,

A reference inverter is to be designed to achieve a delay of 250 ps when driving a 0.2 pF load using a 2.5V power supply. Assume that the threshold voltages of the CMOS technology are VT N =-VT P = 0.75 V, and K'n=60uA/V2, calculate the value of (W/L)n.

How many NFETS is needed to implement the following function with a single CMOS gate (F-BC+AD): Select one: a. 8 b. 4 c. 10 d. 5

Electrical Engineering Below is the Euler graphs for the pull-daun network for a complex CMOS staticgate.please draw the equivalent dval Euler graph for the pull -down network Draw the transistor schematic for the logic gate corresponding to the Euler paths above. Make sure to size the transistors in the gate saraw numbers for each transistor;assume the sizes fr a base inverter" are 2$1 Sketch the stick diagram for the gate abore.Use a single diffusion region for all transistors in a pull-up netuwork or Pul -lown network

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Detail the stages of executing the MOV instructions assuming an 8 bit processor and a 16 bit IR and program memory following a 8 bit pipeline model.

4. Consider the circuit below on the left. a) What logic function does it perform? (What is F in terms of inputs A and B?) b) Find the transistor sizes (NMOS and PMOS widths) so that the fundamental dynamics are that of the symmetrical inverter on the right. VDD Ā- A - B 6W F 3W A В