3. Assume you have a computer where the cycles per Instruction(CPI) is 1 when all the memory accesses hit in the cache. The only data accesses are loads and stores and these total 25% of the instructions.If the miss penalty is 50 clock cycles and the miss rate is 1%, how much faster would the computer if all the instructions were cache hits?

4. Suppose a computer using a fully associative cache has 2^24 byte of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes. a) How big in kilobytes is main memory? b) How big in bytes is cache? In kilobytes? c) How many blocks of main memory are there? d) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? e) To which cache block will the memory address 0x01D8729A map?

Let's pretend the CPU issues a cache request that eventually reaches the cache when a block is being flushed from the write buffer back to main memory. To what extent should this proceed?

A digital computer has a memory unit with 32 bits per word. The instruction set consists of 110 different operations. All instructions have an operation code part (opcode) and two address fields: one for a memory address and one for a register address. This particular system includes eight general-purpose, user-addressable registers. Registers may be loaded directly from memory, and memory may be updated directly from the registers. Direct memory-to-memory data movement operations are not supported. Each instruction stored in one word of memory. At least, how many bits are needed for the opcode?