Database System Concepts
7th Edition
ISBN: 9780078022159
Author: Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher: McGraw-Hill Education
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![**Question:**
A CPU is equipped with a cache. If it takes 5 ns to access the data from the cache and 60 ns to access data from the main memory, what should be the hit ratio if the effective memory access time is 8 ns?
**Answer = ________________%**
**Explanation:**
To find the hit ratio, you can use the formula for effective memory access time:
\[ \text{Effective Access Time (EAT)} = (\text{Hit Ratio} \times \text{Cache Access Time}) + ((1 - \text{Hit Ratio}) \times \text{Main Memory Access Time}) \]
Given:
- Cache Access Time = 5 ns
- Main Memory Access Time = 60 ns
- Effective Access Time = 8 ns
Substitute the values:
\[ 8 = (\text{Hit Ratio} \times 5) + ((1 - \text{Hit Ratio}) \times 60) \]
Solve for Hit Ratio:
1. Expand the equation:
\[ 8 = 5 \times \text{Hit Ratio} + 60 - 60 \times \text{Hit Ratio} \]
2. Combine like terms:
\[ 8 = 60 - 55 \times \text{Hit Ratio} \]
3. Rearrange:
\[ 55 \times \text{Hit Ratio} = 60 - 8 \]
4. Simplify:
\[ 55 \times \text{Hit Ratio} = 52 \]
5. Divide both sides by 55:
\[ \text{Hit Ratio} = \frac{52}{55} \approx 0.9455 \]
Therefore, the hit ratio should be approximately 94.55%.
Fill in the answer:
**Answer = 94.55%**](https://content.bartleby.com/qna-images/question/44c3b237-e4ca-4e38-a278-251c2495f1b6/cac094de-c32e-4f6f-ab71-a115f606d50b/sg35nx_processed.png)
Transcribed Image Text:**Question:**
A CPU is equipped with a cache. If it takes 5 ns to access the data from the cache and 60 ns to access data from the main memory, what should be the hit ratio if the effective memory access time is 8 ns?
**Answer = ________________%**
**Explanation:**
To find the hit ratio, you can use the formula for effective memory access time:
\[ \text{Effective Access Time (EAT)} = (\text{Hit Ratio} \times \text{Cache Access Time}) + ((1 - \text{Hit Ratio}) \times \text{Main Memory Access Time}) \]
Given:
- Cache Access Time = 5 ns
- Main Memory Access Time = 60 ns
- Effective Access Time = 8 ns
Substitute the values:
\[ 8 = (\text{Hit Ratio} \times 5) + ((1 - \text{Hit Ratio}) \times 60) \]
Solve for Hit Ratio:
1. Expand the equation:
\[ 8 = 5 \times \text{Hit Ratio} + 60 - 60 \times \text{Hit Ratio} \]
2. Combine like terms:
\[ 8 = 60 - 55 \times \text{Hit Ratio} \]
3. Rearrange:
\[ 55 \times \text{Hit Ratio} = 60 - 8 \]
4. Simplify:
\[ 55 \times \text{Hit Ratio} = 52 \]
5. Divide both sides by 55:
\[ \text{Hit Ratio} = \frac{52}{55} \approx 0.9455 \]
Therefore, the hit ratio should be approximately 94.55%.
Fill in the answer:
**Answer = 94.55%**
![A CPU is equipped with a cache. If it takes 5 ns to access the data from the cache and 60 ns to access data from the main memory, what is the effective memory access time if the hit ratio is 90%?
Answer = _______________ ns
[Input box]](https://content.bartleby.com/qna-images/question/44c3b237-e4ca-4e38-a278-251c2495f1b6/cac094de-c32e-4f6f-ab71-a115f606d50b/u5uyc2r_processed.png)
Transcribed Image Text:A CPU is equipped with a cache. If it takes 5 ns to access the data from the cache and 60 ns to access data from the main memory, what is the effective memory access time if the hit ratio is 90%?
Answer = _______________ ns
[Input box]
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- On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?arrow_forwardOn the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?arrow_forwardA CPU is equipped with a cache. Accessing a word takes 40 clock cycles if the data is not in the cache and 5 clock cycles if the data is in the cache. What is the effective memory access time in clock cycles if the hit ratio is 80%?arrow_forward
- A CPU's clock rate is 4 GHz. This CPU's cache hit time is measured as 1 clock cycle, the miss penalty is 35 cycles. The cache hit rate is 80%. What's the CPU's clock cycle time measured inns?arrow_forwardOn the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?arrow_forwardA CPU is equipped with a cache. If it takes 4 ns to access the data from the cache and 100 ns to access data from the main memory, what is the effective memory access time if the hit ratio is 95%?arrow_forward
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