1. Implement the following Boolean function by using 4x1 multiplexer. F(A,B, C, D) = Em(1,3,5,6,8,11,14)
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- Design a 4-bit BCD to Gray Code Converter by using Programmable Array logic.A multiplexer a.Takes a single data input and routes it to one of several outputs b.Selects from many data sources c.converts a binary code input to a single output d.converts a single input to a binary codeparity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.
- Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- Cin Cout Figure Q4(a)(ii)Design a combinational circuit with the four inputs A,B.C, and D, and three outputs X, Y, and Z. When the binary input is odd number, the binary output is one lesser than the input. When the binary input is even number the binary output is one greate than the input. Implement the function using multiplexers with minimal input and select line.Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- B Cin Cout Figure Q4(a)(ii) (iii) Given A = 111001 and B = 100010. Construct a 6-bit parallel adder to solve for A + B.
- To implement a Full Subtracter, Using TWO 8:1 Multiplexers (ONE for Sum output and ONE for Cout output). Assign (or Connect) X, Y,and Bin variables to the Select Inputs of Multiplexers and connect 1 or 0 to each Data Input.By using the design procedure for digital computers, design the following:i. Encoderii. Decoderiii. 4-bit comparatora) Design Binary Ripple Counter using D-flipflop. b) Design asynchronous 4-bit UP-Down counter.
- d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.The upper 16 -bit binary count value are displayed on the four seven -segemnt displays as four hexadecimal digits. Hexadecimal values aren't good for human perception. How would you suggest the counter design be modified so that only decimal count values are displayed.Q2) A) Express the decimal number (- 30 ) as an 8-bit number in 2's complement form, and verifying its decimal value. B) Design an Octal-to-Binary (8-to-3) Encoder, and then draw a block diagram for Octal-to- Binary Encoder.