2. Consider the following Boolean function: F = ā + a(c+b)(b+c). (a) build the truth table for the pull-up network. (b) build the truth table for the pull-down network. (c) build the truth table for F.

Please design a 6:1 multiplexer following the below procedures with data inputs of D5, D4, D3,D2, D1, D0 and output of Y.1 How many select signals are needed for this Mux.2) List a truth table for this Mux. Note: for all the unused combinations of select signals, Y=D5Develop an optimized function for this Mux.4Sketch the logic diagram of implementing this 6:1 Mux. Write a complete VHDL structural model to implement the above 6:1 multiplexer. Assume allthe required sub-component (standard gates) VHDL models are given/known that you can use.

File name: Mystery.asm In this exercise, you will be creating a 4-variable K-map to minimize the logic for the truth table below. From the minimized K- map, please write the HDL code using standard, built-in chips, such as (And, Not, Or, XOr, Mux, DMux). BCD Out 00000 OO100 0100 0 O1100 B0000 30011 1011 : 1011 B110 0

For the following question, you need to create a truth table, write the Boolean expression for each output based on the truth table, use K-map to simplify the expression if possible, and draw the logic diagram using AND, OR, NOT gate only. 1. Design a 3-bit shifter. a. A0, A1, A2, and S as inputs b. If S=0, then shift one bit to the left and add 0 to the last bit c. If S=1, then shift one bit to the right and add 0 to the first bit d. Y0, Y1, and Y2 as outputs

4. (a) Develop a truth table of the following flipflop: PRE R CLR 4(b) How to convert a JK flip flop into T flipflop? Explain an application of a JK flipflop.