Please design a 6:1 multiplexer following the below procedures with data inputs of D5, D4, D3, D2, D1, D0 and output of Y. 1 How many select signals are needed for this Mux. 2) List a truth table for this Mux. Note: for all the unused combinations of select signals, Y=D5 Develop an optimized function for this Mux.

Electric Motor Control

10th Edition

ISBN:9781133702818

Author:Herman

Publisher:Herman

Chapter22: Sequence Control

Section: Chapter Questions

Problem 6SQ: Draw a symbol for a solid-state logic element AND.

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Concept explainers

Latches and Flip Flop

Just like logic gates, the latches and flip-flops are the important elements of an electronic circuit. The logic gates form the important part of combinatorial circuits, while the latches and flip-flops form the essential part of a sequential circuit. Sequential circuits form the important concept of automata theory in electronics and electrical engineering, these circuits are a kind of logic circuit whose output depends on both present input and past inputs, that is, the input history.

Question

Please design a 6:1 multiplexer following the below procedures with data inputs of D5, D4, D3,
D2, D1, D0 and output of Y.
1 How many select signals are needed for this Mux.
2) List a truth table for this Mux. Note: for all the unused combinations of select signals, Y=D5
Develop an optimized function for this Mux.
4Sketch the logic diagram of implementing this 6:1 Mux.
Write a complete VHDL structural model to implement the above 6:1 multiplexer. Assume all
the required sub-component (standard gates) VHDL models are given/known that you can use.

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Step 1: what is given and what to do:

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Step 2: Part 1 - finding the number of select lines:

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Step 3: Part 2 - Finding the truth table:

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Step 4: Part 3 - finding the optimized boolean function:

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