2) Write a ALP to implement an NOR gate and store the result in the memory location 8000H.

187. ON OUREX For the logic network shown in FIGURE Q2(c): C. 08TCD B 081OZ OBIOZ 09102 i. ii. EDB1034 67X1 d CD NYXH AL B + CD NVD NV H A FIGURE Q2(c) Derive the corresponding truth table. A(B + CD) Convert the logic network into a NAND-gate only implementation. Convert the logic network into a NOR-gate only implementation. 08102 MED MIXE D OSTO NVD D8102 NVE NVXI Al 18102 NVE NVXI ALI DORIOZ NVP NVXN DATO

4 use eqation as show in picture design logic circuir ?   4.1 use NAND only    4.2 use NOR only

Problem No. 1. Using mesh analysis, solve for Vo. B=100 9 Volts Vb Rb 20 KOhms Rc 500 Ohms с V₁ =? Vcc 2 Volts

5. Write a 1-page summary (typed, 1.5 spaced) of the fabrication process for a silicon CMOS inverter

find the output of each gate (OR - AND-NOT-NOR- NAND -XOR) by using 3 inputs (A,B,C)?

2.

There is 180 degree phase displacement between two SCR gate signals in single phase half bridge inverter. Select one: O True O False