1. What is the difference (or differences) between a TLB and on-chip cache? a. The TLB is direct-mapped, while caches are set associative. b. The TLB is indexed by the virtual address, while caches are Indexed by the physical address. c. The TLB stores virtual-to-physical address transiations, while caches store data. d. The TLB can be slow, but caches need to be fast. e. The TLB stores instructions, while caches store data. 2. Say we have two mutexes, implemented with binary semaphores, and two threads which access them. Which of the following can cause deadlock. a. The threads lock the mutexes in the same order. b. The threads lock the mutexes in a different order. C. The threads unlock the mutexes in the same order. d. The threads uniock the mutexes in a different order.

1. What is the difference (or differences) between a TLB and on-chip cache? a. The TLB is direct-mapped, while caches are set associative. b. The TLB is indexed by the virtual address, while caches are Indexed by the physical address. c. The TLB stores virtual-to-physical address transiations, while caches store data. d. The TLB can be slow, but caches need to be fast. e. The TLB stores instructions, while caches store data. 2. Say we have two mutexes, implemented with binary semaphores, and two threads which access them. Which of the following can cause deadlock. a. The threads lock the mutexes in the same order. b. The threads lock the mutexes in a different order. C. The threads unlock the mutexes in the same order. d. The threads uniock the mutexes in a different order.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 21VE

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Similar questions

Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative cache with cache block size of 16 bytes. a. What is the number of sets in the cache? b. What is the size (in bits) of the tag field per cache block? c. What is the number and size of comparators required for tag matching? d. How many address bits are required to find the byte offset within a cache block? e. What is the total amount of extra memory (in bytes) required for the tag bits?
5. Suppose a byte-addressable computer using set-associate cache has 2^21 bytes of main memory and a cache of 64 blocks, where each cache block contains 16 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?  b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?   Show all work and explain how you got the answers please. Thanks
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes.  a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?  b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
Suppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.                                            a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
1. For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache. Tag Index Offset 31-14 13-7 6-0 a. What is the cache block size (in words)? b. How many entries does this cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Suppose a computer using fully associative cache has 4G bytes of byte-addressable main memory and a cache of 512 blocks, where each cache block contains 128 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0x018072 map?
Suppose a computer using direct mapped cache has 4G Bytes of main memory and a cache of 256 Blocks, where each cache Block has 16 Words, and Word Size is 4 Bytes. a)How many blocks of main memory? b)What is the format of a memory address as seen by the cache (Tag, Block and Word fields)? c)To which cache block will the memory reference 0000146A in Hex?
For a direct-mapped cache design with 64-bit addresses, the following bits of the address are used to access the cache: Tag Index Offset 63-13 12-4 3-0 a. What is the cache block size (in bytes)?b. What is the cache size (in bytes)?c. What is the total number of bits (including valid bit, tag bits and data array bits) to implement this cache?d. For the same block and cache sizes, you want to implement a 4-way set-associative cache, what is the number of index bit and the number of tag bits?
A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words.i) How many bits are there in the tag, index, block and word fields of the address format?ii) How many bits are there in each word of cache, and how are they divided into functions? Include a valid bit.iii) How many blocks can the cache accommodate?
You play the role of the instructor of CPSC440. Your CPSC440 students need more practice on the cache memory concept. You, as a professor of the CPSC440 course, decide to solve one more cache memory access problem (in addition to two problems in our Assignment). The new problem is: You are given a direct-mapped cache of 4 blocks with four-word per block (a total of 16 words in the cache). The main memory size is 64 words. We have the following memory access sequence: Word1, Word 8, Word0, Word 17, Word 14, Word 62, Word 55, Word 25, Word 16, and Word 15. You need to write an essay that explains how you solve this problem. You also need to show your students the final cache content using the given table shown below.You also need to explain to your students the result of hit or miss for each word access.