1. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates? a) AND or OR gates b) XOR or XNOR gates c) NOR or NAND gates d) AND or NOR gates 2. In S-R flip-flop, if Q = 0 the output is said to be a) Set b) Reset c) Previous state d) Current state 3. What is one disadvantage of an S-R flip-flop? a) It has no Enable input c) It has no clock input b) It has a RACE condition d) Invalid State 4. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fn) to the first flip-flop is 32 kHz, the output frequency (fout) is a) 1 kHz b) 2 kHz c) 4 kHz d) 16 kHz 5. In D flip-flop, D stands for a) Distant b) Data c) Desired d) Delay 6. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs? a) The output increases by 1 c) The output word increases by 2 b) The output decreases by 1 d) The output word decreases by 2 7. How many flip-flops are required to construct a decade counter? a) 4 b) 8 c) 5 d) 10 8. Three cascaded decade counters will divide the input frequency by d) 1000 а) 10 b) 20 c) 100 9. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first) a) 1100 b) 0011 c) 0000 d) 1111 10. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in a) 4 us b) 40 µs c) 400 us d) 40 ms
1. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates? a) AND or OR gates b) XOR or XNOR gates c) NOR or NAND gates d) AND or NOR gates 2. In S-R flip-flop, if Q = 0 the output is said to be a) Set b) Reset c) Previous state d) Current state 3. What is one disadvantage of an S-R flip-flop? a) It has no Enable input c) It has no clock input b) It has a RACE condition d) Invalid State 4. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fn) to the first flip-flop is 32 kHz, the output frequency (fout) is a) 1 kHz b) 2 kHz c) 4 kHz d) 16 kHz 5. In D flip-flop, D stands for a) Distant b) Data c) Desired d) Delay 6. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs? a) The output increases by 1 c) The output word increases by 2 b) The output decreases by 1 d) The output word decreases by 2 7. How many flip-flops are required to construct a decade counter? a) 4 b) 8 c) 5 d) 10 8. Three cascaded decade counters will divide the input frequency by d) 1000 а) 10 b) 20 c) 100 9. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first) a) 1100 b) 0011 c) 0000 d) 1111 10. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in a) 4 us b) 40 µs c) 400 us d) 40 ms
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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Transcribed Image Text:Q1: Choose the best answer that completes the statement or answers the question.
1. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
2. In S-R flip-flop, if Q = 0 the output is said to be
a) Set
b) Reset
c) Previous state
d) Current state
3. What is one disadvantage of an S-R flip-flop?
a) It has no Enable input
c) It has no clock input
b) It has a RACE condition
d) Invalid State
4. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to
the first flip-flop is 32 kHz, the output frequency (fout) is
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
5. In D flip-flop, D stands for
a) Distant
b) Data
c) Desired
d) Delay
6. What happens to the parallel output word in an asynchronous binary down counter whenever a
clock pulse occurs?
a) The output increases by 1
c) The output word increases by 2
b) The output decreases by 1
d) The output word decreases by 2
7. How many flip-flops are required to construct a decade counter?
a) 4
b) 8
c) 5
d) 10
8. Three cascaded decade counters will divide the input frequency by
d) 1000
a) 10
b) 20
c) 100
9. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble
1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111
10. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
a) 4 µs
b) 40 µs
c) 400 us
d) 40 ms
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