V dd Q1 Q2 Q5 Q3 A - Output Q4 Q6 B Write down the truth table for above logic gate with the ON / OFF status of each MOSFET and identify the gate.

Design a CMOS logic gate that implements the following function: �=�*�*�+� Then perform the basic layout of circuit (draw the stick diagram).

A circuit in Figure Q.2a compares 2-bit binary numbers, P and Q represented by PiPo and QiQo respectively. Note that Po and Qo are LSB. (a) Determine under which condition Z will be '1'. (b) Redesign the circuit using active-high 4-to-16 decoder and a logic gate. Z P1 Q1 Figure 2a Po Qo D

1.1 Given the timing diagram for 3-bit input A and two outputs, S and C in Figure la, where A2 is the MSB and Ao is the LSB. Assume the output for the other input conditions is don't cares (i.c. X). Determine the minimum logic circuit using NAND logic configuration. Az Ac S C Figure la