Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Question
Chapter 4.4, Problem 4.28PP
A.
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch should be taken or not in a jump instruction.
- Memory:
- The data is been written to memory or read from memory in this stage.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
B.
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch should be taken or not in a jump instruction.
- Memory:
- The data is been written to memory or read from memory in this stage.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
C.
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch should be taken or not in a jump instruction.
- Memory:
- The data is been written to memory or read from memory in this stage.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
D.
Program Plan Intro
Processing stages:
- The processing of an instruction has number of operations.
- The operations are organized into particular sequence of stages.
- It attempts to follow a uniform sequence for all instructions.
- The description of stages are shown below:
- Fetch:
- It uses program counter “PC” as memory address to read instruction bytes from memory.
- The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.
- It fetches “valC” that denotes an 8-byte constant.
- It computes “valP” that denotes value of “PC” plus length of fetched instruction.
- Decode:
- The register file is been read with two operands.
- It gives values “valA” and “valB” for operands.
- It reads registers with instruction fields “rA” and “rB”.
- Execute:
- In this stage the ALU either performs required operation or increments and decrements stack pointer.
- The resulting value is termed as “valE”.
- The condition codes are evaluated and destination register is updated based on condition.
- It determines whether branch should be taken or not in a jump instruction.
- Memory:
- The data is been written to memory or read from memory in this stage.
- The value that is read is determined as “valM”.
- Write back:
- The results are been written to register file.
- It can write up to two results.
- PC update:
- The program counter “PC” denotes memory address to read bytes of instruction from memory.
- It is used to set next instruction’s address.
- Fetch:
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Problem I ( Assembler )
Provide the assembly implementation of the C - code below . Sub 10 is a function that subtract 10 from a given input x.
Assumption :
MyArray base address is store in register $S1.
Feel free to use instruction li or si.
li load an immediate value into a register . For instance, li $S4 5 will copy value 5 into register $S4.
C code
for ( i = 0,1 < 10 , i ++ )
{
MyArray [ i ] = MyArray [ i - 1 ] + MyArray [ i + 1 ] ;
Sub10 ( MyArray [ i ];
}
Sub10 ( x )
{
Return ( x - 10 ) ;
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Code in Assembly Language:
sub10(int): ; Implementation of the sub10() function
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mov DWORD PTR [rbp-4], edi
mov eax, DWORD PTR [rbp-4]
sub eax, 10
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Problem I ( Assembler )
Provide the assembly implementation of the C - code below . Sub 10 is a function that subtract 10 from a given input x.
Assumption :
MyArray base address is store in register $S1.
Feel free to use instruction li or si.
li load an immediate value into a register . For instance, li $S4 5 will copy value 5 into register $S4.
C code
for ( i = 0,1 < 10 , i ++ )
{
MyArray [ i ] = MyArray [ i - 1 ] + MyArray [ i + 1 ] ;
Sub10 ( MyArray [ i ];
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Sub10 ( x )
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Chapter 4 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 4.1 - Prob. 4.1PPCh. 4.1 - Prob. 4.2PPCh. 4.1 - Prob. 4.3PPCh. 4.1 - Prob. 4.4PPCh. 4.1 - Prob. 4.5PPCh. 4.1 - Prob. 4.6PPCh. 4.1 - Prob. 4.7PPCh. 4.1 - Prob. 4.8PPCh. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP
Ch. 4.2 - Prob. 4.11PPCh. 4.2 - Prob. 4.12PPCh. 4.3 - Prob. 4.13PPCh. 4.3 - Prob. 4.14PPCh. 4.3 - Prob. 4.15PPCh. 4.3 - Prob. 4.16PPCh. 4.3 - Prob. 4.17PPCh. 4.3 - Prob. 4.18PPCh. 4.3 - Prob. 4.19PPCh. 4.3 - Prob. 4.20PPCh. 4.3 - Prob. 4.21PPCh. 4.3 - Prob. 4.22PPCh. 4.3 - Prob. 4.23PPCh. 4.3 - Prob. 4.24PPCh. 4.3 - Prob. 4.25PPCh. 4.3 - Prob. 4.26PPCh. 4.3 - Prob. 4.27PPCh. 4.4 - Prob. 4.28PPCh. 4.4 - Prob. 4.29PPCh. 4.5 - Prob. 4.30PPCh. 4.5 - Prob. 4.31PPCh. 4.5 - Prob. 4.32PPCh. 4.5 - Prob. 4.33PPCh. 4.5 - Prob. 4.34PPCh. 4.5 - Prob. 4.35PPCh. 4.5 - Prob. 4.36PPCh. 4.5 - Prob. 4.37PPCh. 4.5 - Prob. 4.38PPCh. 4.5 - Prob. 4.39PPCh. 4.5 - Prob. 4.40PPCh. 4.5 - Prob. 4.41PPCh. 4.5 - Prob. 4.42PPCh. 4.5 - Prob. 4.43PPCh. 4.5 - Prob. 4.44PPCh. 4 - Prob. 4.45HWCh. 4 - Prob. 4.46HWCh. 4 - Prob. 4.47HWCh. 4 - Prob. 4.48HWCh. 4 - Modify the code you wrote for Problem 4.47 to...Ch. 4 - In Section 3.6.8, we saw that a common way to...Ch. 4 - Prob. 4.51HWCh. 4 - The file seq-full.hcl contains the HCL description...Ch. 4 - Prob. 4.53HWCh. 4 - The file pie=full. hcl contains a copy of the PIPE...Ch. 4 - Prob. 4.55HWCh. 4 - Prob. 4.56HWCh. 4 - Prob. 4.57HWCh. 4 - Our pipelined design is a bit unrealistic in that...Ch. 4 - Prob. 4.59HW
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