Activities Manual for Programmable Logic Controllers
5th Edition
ISBN: 9781259679568
Author: Petruzella, Frank
Publisher: MCGRAW-HILL HIGHER EDUCATION
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Question
Chapter 1, Problem 20RQ
Program Plan Intro
Programmable Logic Controller (PLC):
- • Programmable Logic Controller (PLC) is a specialized computer used in industrial segments to control machines and process.
- • PLC is program that consists of a set of instructions which resembles the controlling functions needed to perform specific tasks.
- • The function of PLC is similar to that of a relay and hence, in an industrial segment a relay is greatly replaced by a suitable PLC.
- • When compared to general PC, a PLC is available in small and tiny sizes.
- • The basic architecture of a PLC consists of an input-output interface module and a small Central Processing Unit (CPU) that runs by control
programming language.
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Students have asked these similar questions
What is the key difference between programmable input/output (I/O) and interrupt-driven I/O?
Q2
Design a controller for 4-bit computer using the given table. (assume instruction register size is 10 bit)
Opcode Binary Representation
LDA 10010
ADD 10110
SUB 11111
OUT 01101
HLT 00001
(d) The table below shows the ALUcontrol signal of the datapath we discussed in class.
Instruction
Funct
ALU
Орсode
ALUop
ALU action
operation
field
control
Iw
00
load word
XXXXXX
add
0010
Sw
00
store word
XXXXXX
add
0010
beq
01
branch equal
subtract
0110
XXXXXX
R-type
10
add
100000
add
0010
R-type
10
subtract
100010
subtract
0110
R-type
10
AND
100100
AND
0000
R-type
10
OR
100101
OR
0001
R-type
10
set on less than
101010
set on less than
0111
You want to add the bne instruction into the datapath, which already includes the
required hardware for the instruction. Write out the ALUop for bne and how you can
determine whether the bne results in the branch to be taken.
Chapter 1 Solutions
Activities Manual for Programmable Logic Controllers
Ch. 1 - Prob. 1RQCh. 1 - Identify four tasks in addition to relay switching...Ch. 1 - Prob. 3RQCh. 1 - Prob. 4RQCh. 1 - Prob. 5RQCh. 1 - Prob. 6RQCh. 1 - Explain the main function of each of the following...Ch. 1 - What are the two most common types of PLC...Ch. 1 - Prob. 9RQCh. 1 - Prob. 10RQ
Ch. 1 - Answer the following with reference to the process...Ch. 1 - Prob. 12RQCh. 1 - Answer the following with reference to the process...Ch. 1 - Prob. 14RQCh. 1 - Compare the PLC and PC with regard to: a. Physical...Ch. 1 - Prob. 16RQCh. 1 - Prob. 17RQCh. 1 - Prob. 18RQCh. 1 - Prob. 19RQCh. 1 - Prob. 20RQCh. 1 - List five factors affecting the memory size needed...Ch. 1 - Prob. 22RQCh. 1 - Given two single-pole switches, write a program...Ch. 1 - Given two single-pole switches, write a program...Ch. 1 - Prob. 3PCh. 1 - Prob. 4PCh. 1 - Prob. 5P
Knowledge Booster
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- Draw a basic logic diagram for a 512 × 8-bit static RAM, showing all the inputs and outputs.arrow_forwardUsing four 32 x 8 ROM chips, design a circuit such that the effective size of the ROM circuit is 64 x 16. The ROM chip must show the Address inputs, enable input, and data connections. As shown in the lessons, use the MSB(s) of the combined address lines as the chip selection lines.arrow_forwardThe interrupt vector table is made up of many entries, each of which has its own independent data structure.arrow_forward
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- Category: CPU Wiring Look at the following (incomplete) diagram of the Hack CPU taken from figure 5.9 of the textbook. ALU output outM instruction AM inM writeM A addressM inc reset PC po Match the wires A, B, C, D and E with the logic expression that describes the signal they should carry. The logic expressions use the operators not (!), and (&&) and or (I). The 16 wire instruction is named instr. The A and C instruction formats are: A-instruction: 0 V. V. V C-instruction: 1 1 1 a c1 c2 c3 c5 c6 d1 d2 d3 j1 j2 j3 Mire number: 15 14 13 12 11 10 9 8 6. 4 3 1 instr[15) && instr[3] B. instr[14] ALUarrow_forwardFor computers based On three address instruction fonnats, each adbess field can be used to specify which of the foilowing SI: A memory operand Sh A processor register S3: An implied accumulator tregisterarrow_forwardThe outputs of four registers, A, B, C, D, H, L are connected through 8:1 line multiplexer to the input of a fifth register, X. Each register is 16 bits long. The required transfers are dictated by four timing variables, T0 through T3 as follows: T0 : X←A T1 : X←B T2 : X←C T3 : X←D The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the others are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register X.arrow_forward
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